- 06 Sep, 2021 4 commits
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Minyong Li authored
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Minyong Li authored
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Minyong Li authored
This stops at the middle of memory write back.
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Minyong Li authored
The binary representation is correct.
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- 29 Aug, 2021 1 commit
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Minyong Li authored
91d71c41 already includes the memory load instructions. In addition, these bind statements do not work well with a few tools I use. This reverts commit d7827bd8.
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- 23 Aug, 2021 11 commits
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Minyong Li authored
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Minyong Li authored
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Minyong Li authored
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Minyong Li authored
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Minyong Li authored
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Minyong Li authored
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Minyong Li authored
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Minyong Li authored
This may be further expanded into an ALU test.
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Minyong Li authored
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Minyong Li authored
Chisel UInt conversion from/to aggregates involves reversal. This causes problem for the Quarter Rounds, since they receive wrong bits, leading to completely different results (which are wrong).
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Minyong Li authored
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- 22 Aug, 2021 1 commit
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Minyong Li authored
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- 21 Aug, 2021 7 commits
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Minyong Li authored
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Minyong Li authored
Particularly: firrtl_black_box_resource_files.f
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Minyong Li authored
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Minyong Li authored
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Minyong Li authored
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Minyong Li authored
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Minyong Li authored
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- 22 Jul, 2021 2 commits
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Minyong Li authored
This may be used to interrupt an external controller.
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Minyong Li authored
There is now only a 'halt' signal that stops the processor.
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- 13 Jul, 2021 1 commit
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Minyong Li authored
Now Read-After-Write gives old data (Read-First). Quartus does not give warnings. No bypass logic is implemented.
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- 12 Jul, 2021 2 commits
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Minyong Li authored
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Minyong Li authored
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- 11 Jul, 2021 7 commits
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Minyong Li authored
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Minyong Li authored
Two simultaneous read causes Quartus to synthesize additional BRAM and is unnecessary. This commit attempts to make Quartus to infer a Simple Dual-Port RAM. Plus a take pin exposed from CanCore, which can be used to take control on both of the memories.
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Minyong Li authored
This version of core uses a more RISC-like architecture. - a register file is added - unused configs and signals are removed - various changes
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Minyong Li authored
This reverts 585b1228.
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Minyong Li authored
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Minyong Li authored
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Minyong Li authored
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- 08 Jul, 2021 3 commits
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Minyong Li authored
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Minyong Li authored
... as a preparation of architecture refactor.
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Minyong Li authored
Architectural change: the flattened columnar round and diagonal round are now stacked and controlled by a signal, which means only one can be activated now.
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- 07 Jul, 2021 1 commit
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Minyong Li authored
An addition is trivially synthesized to a ripple-carry adder. With 512b + 512b the carry chain is super long and delay becomes super high. Although the results are same, now just use 16 32b ripple- carry adders, which is also what the standards specify. Later a faster adder may be considered.
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