This stops at the middle of memory write back.

The binary representation is correct.

91d71c41 already includes the memory load instructions. In addition,
these bind statements do not work well with a few tools I use.

This reverts commit d7827bd8.

This may be further expanded into an ALU test.

Chisel UInt conversion from/to aggregates involves reversal. This
causes problem for the Quarter Rounds, since they receive wrong
bits, leading to completely different results (which are wrong).

Particularly: firrtl_black_box_resource_files.f

This may be used to interrupt an external controller.

There is now only a 'halt' signal that stops the processor.

Now Read-After-Write gives old data (Read-First). Quartus does not
give warnings. No bypass logic is implemented.

Two simultaneous read causes Quartus to synthesize additional BRAM
and is unnecessary. This commit attempts to make Quartus to infer
a Simple Dual-Port RAM.

Plus a take pin exposed from CanCore, which can be used to take
control on both of the memories.

This version of core uses a more RISC-like architecture.

- a register file is added
- unused configs and signals are removed
- various changes

This reverts 585b1228.

... as a preparation of architecture refactor.

Architectural change: the flattened columnar round and diagonal
round are now stacked and controlled by a signal, which means only
one can be activated now.

An addition is trivially synthesized to a ripple-carry adder. With
512b + 512b the carry chain is super long and delay becomes super
high. Although the results are same, now just use 16 32b ripple-
carry adders, which is also what the standards specify. Later a
faster adder may be considered.