Administrator approval is now required for registering new accounts. If you are registering a new account, and are external to the University, please ask the repository owner to contact ServiceLine to request your account be approved. Repository owners must include the newly registered email address, and specific repository in the request for approval.

The University Git service will be offline on Wednesday December 1st 2021, between 08:00am - 09:00am to complete a required scheduled change. Please ensure that you do not make any changes or commits to your projects/repositories during this time as these changes may be lost.

Verified Commit ba9d911c authored by Minyong Li's avatar Minyong Li 💬
Browse files

core.ALU: add bypass funcs

parent 03be9282
......@@ -42,7 +42,9 @@ class ALU(implicit cfg: CanCoreConfiguration) extends MultiIOModule {
CanCoreALUFunction.columnarRound.U -> columnarRound.out,
CanCoreALUFunction.diagonalRound.U -> diagonalRound.out,
CanCoreALUFunction.add.U -> adder.out,
CanCoreALUFunction.xor.U -> xorer.out
CanCoreALUFunction.xor.U -> xorer.out,
CanCoreALUFunction.a.U -> a,
CanCoreALUFunction.b.U -> b
......@@ -4,9 +4,9 @@
import chisel3._
import chisel3.util.{MuxLookup, log2Ceil}
import chisel3.util.log2Ceil
class ProgramMemory(implicit cfg: CanCoreConfiguration) extends MultiIOModule {
private val addrWidth = log2Ceil(cfg.programMemoryWords)
......@@ -8,6 +8,8 @@ case object CanCoreALUFunction {
val diagonalRound = 3
val add = 4
val xor = 5
val a = 6
val b = 7
def requiredWidth = log2Ceil(xor)
def requiredWidth = log2Ceil(b)
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment