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Verified Commit ba9d911c authored by Minyong Li's avatar Minyong Li 💬
Browse files

core.ALU: add bypass funcs

parent 03be9282
......@@ -42,7 +42,9 @@ class ALU(implicit cfg: CanCoreConfiguration) extends MultiIOModule {
CanCoreALUFunction.columnarRound.U -> columnarRound.out,
CanCoreALUFunction.diagonalRound.U -> diagonalRound.out,
CanCoreALUFunction.add.U -> adder.out,
CanCoreALUFunction.xor.U -> xorer.out
CanCoreALUFunction.xor.U -> xorer.out,
CanCoreALUFunction.a.U -> a,
CanCoreALUFunction.b.U -> b
)
)
}
......@@ -4,9 +4,9 @@
package uk.ac.soton.ecs.can.core
import chisel3._
import chisel3.util.{MuxLookup, log2Ceil}
import uk.ac.soton.ecs.can.types._
import chisel3.util.log2Ceil
import uk.ac.soton.ecs.can.config.CanCoreConfiguration
import uk.ac.soton.ecs.can.types._
class ProgramMemory(implicit cfg: CanCoreConfiguration) extends MultiIOModule {
private val addrWidth = log2Ceil(cfg.programMemoryWords)
......
......@@ -8,6 +8,8 @@ case object CanCoreALUFunction {
val diagonalRound = 3
val add = 4
val xor = 5
val a = 6
val b = 7
def requiredWidth = log2Ceil(xor)
def requiredWidth = log2Ceil(b)
}
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