Administrator approval is now required for registering new accounts. If you are registering a new account, and are external to the University, please ask the repository owner to contact ServiceLine to request your account be approved. Repository owners must include the newly registered email address, and specific repository in the request for approval.

The University Git service will be offline on Wednesday December 1st 2021, between 08:00am - 09:00am to complete a required scheduled change. Please ensure that you do not make any changes or commits to your projects/repositories during this time as these changes may be lost.

Verified Commit 9a4dc499 authored by Minyong Li's avatar Minyong Li 💬
Browse files

core.CanCore: add halted output signal

This may be used to interrupt an external controller.
parent 2b87115f
Pipeline #7477 passed with stage
in 3 minutes and 1 second
......@@ -21,6 +21,8 @@ class CanCore(implicit cfg: CanCoreConfiguration) extends MultiIOModule {
val io = IO(new Bundle {
val take = Input(Bool())
val halted = Output(Bool())
val programMemory = new Bundle {
val read =
new MemoryReadIO(programMemoryAddressWidth, programMemoryDataWidth)
......@@ -46,7 +48,9 @@ class CanCore(implicit cfg: CanCoreConfiguration) extends MultiIOModule {
private val ctrl = programMemory.read.data.asTypeOf(new CanCoreControlWord)
programMemory.halt := Mux(io.take, io.take, ctrl.halt)
private val halt = Mux(io.take, io.take, ctrl.halt)
io.halted := halt
programMemory.halt := halt
dataMemory.read.addr := Mux(
io.take,
......
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment