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Verified Commit 1325f446 authored by Minyong Li's avatar Minyong Li :speech_balloon:
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MemoryReadIO: remove read enable

This reverts 585b1228.
parent 41900e5b
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...@@ -20,9 +20,7 @@ class DataMemory(implicit cfg: CanCoreConfiguration) extends MultiIOModule { ...@@ -20,9 +20,7 @@ class DataMemory(implicit cfg: CanCoreConfiguration) extends MultiIOModule {
else else
Mem(cfg.dataMemoryWords, UInt(512.W)) Mem(cfg.dataMemoryWords, UInt(512.W))
when(read.en) { read.data := mem(read.addr)
read.data := mem(read.addr)
}
when(write.en) { when(write.en) {
mem(write.addr) := write.data mem(write.addr) := write.data
......
...@@ -40,9 +40,7 @@ class ProgramMemory(implicit cfg: CanCoreConfiguration) extends MultiIOModule { ...@@ -40,9 +40,7 @@ class ProgramMemory(implicit cfg: CanCoreConfiguration) extends MultiIOModule {
cw := mem(pc) cw := mem(pc)
when(read.en) { read.data := mem(read.addr)
read.data := mem(read.addr)
}
when(write.en) { when(write.en) {
mem(write.addr) := write.data mem(write.addr) := write.data
......
...@@ -6,7 +6,6 @@ package uk.ac.soton.ecs.can.types ...@@ -6,7 +6,6 @@ package uk.ac.soton.ecs.can.types
import chisel3._ import chisel3._
class MemoryReadIO(addrWidth: Int, dataWidth: Int) extends Bundle { class MemoryReadIO(addrWidth: Int, dataWidth: Int) extends Bundle {
val en = Input(Bool())
val addr = Input(UInt(addrWidth.W)) val addr = Input(UInt(addrWidth.W))
val data = Output(UInt(dataWidth.W)) val data = Output(UInt(dataWidth.W))
} }
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