From 1325f446041f859bc0e1b0cefc91da8576365ce0 Mon Sep 17 00:00:00 2001 From: Minyong Li <ml10g20@soton.ac.uk> Date: Sun, 11 Jul 2021 17:25:28 +0100 Subject: [PATCH] MemoryReadIO: remove read enable This reverts 585b122. --- src/main/scala/uk/ac/soton/ecs/can/core/DataMemory.scala | 4 +--- src/main/scala/uk/ac/soton/ecs/can/core/ProgramMemory.scala | 4 +--- src/main/scala/uk/ac/soton/ecs/can/types/MemoryReadIO.scala | 1 - 3 files changed, 2 insertions(+), 7 deletions(-) diff --git a/src/main/scala/uk/ac/soton/ecs/can/core/DataMemory.scala b/src/main/scala/uk/ac/soton/ecs/can/core/DataMemory.scala index 074a29a..8244854 100644 --- a/src/main/scala/uk/ac/soton/ecs/can/core/DataMemory.scala +++ b/src/main/scala/uk/ac/soton/ecs/can/core/DataMemory.scala @@ -20,9 +20,7 @@ class DataMemory(implicit cfg: CanCoreConfiguration) extends MultiIOModule { else Mem(cfg.dataMemoryWords, UInt(512.W)) - when(read.en) { - read.data := mem(read.addr) - } + read.data := mem(read.addr) when(write.en) { mem(write.addr) := write.data diff --git a/src/main/scala/uk/ac/soton/ecs/can/core/ProgramMemory.scala b/src/main/scala/uk/ac/soton/ecs/can/core/ProgramMemory.scala index ca27c96..3d83ead 100644 --- a/src/main/scala/uk/ac/soton/ecs/can/core/ProgramMemory.scala +++ b/src/main/scala/uk/ac/soton/ecs/can/core/ProgramMemory.scala @@ -40,9 +40,7 @@ class ProgramMemory(implicit cfg: CanCoreConfiguration) extends MultiIOModule { cw := mem(pc) - when(read.en) { - read.data := mem(read.addr) - } + read.data := mem(read.addr) when(write.en) { mem(write.addr) := write.data diff --git a/src/main/scala/uk/ac/soton/ecs/can/types/MemoryReadIO.scala b/src/main/scala/uk/ac/soton/ecs/can/types/MemoryReadIO.scala index b0d6f81..4d16411 100644 --- a/src/main/scala/uk/ac/soton/ecs/can/types/MemoryReadIO.scala +++ b/src/main/scala/uk/ac/soton/ecs/can/types/MemoryReadIO.scala @@ -6,7 +6,6 @@ package uk.ac.soton.ecs.can.types import chisel3._ class MemoryReadIO(addrWidth: Int, dataWidth: Int) extends Bundle { - val en = Input(Bool()) val addr = Input(UInt(addrWidth.W)) val data = Output(UInt(dataWidth.W)) } -- GitLab