diff --git a/src/main/scala/uk/ac/soton/ecs/can/core/DataMemory.scala b/src/main/scala/uk/ac/soton/ecs/can/core/DataMemory.scala
index 074a29ab08c92bf95606305349793a8e94976630..824485402954068c56d279459f08c394a50c8428 100644
--- a/src/main/scala/uk/ac/soton/ecs/can/core/DataMemory.scala
+++ b/src/main/scala/uk/ac/soton/ecs/can/core/DataMemory.scala
@@ -20,9 +20,7 @@ class DataMemory(implicit cfg: CanCoreConfiguration) extends MultiIOModule {
     else
       Mem(cfg.dataMemoryWords, UInt(512.W))
 
-  when(read.en) {
-    read.data := mem(read.addr)
-  }
+  read.data := mem(read.addr)
 
   when(write.en) {
     mem(write.addr) := write.data
diff --git a/src/main/scala/uk/ac/soton/ecs/can/core/ProgramMemory.scala b/src/main/scala/uk/ac/soton/ecs/can/core/ProgramMemory.scala
index ca27c9680a1c040edcecf2501c3195cd80e22b66..3d83ead6c8ab4ca4538e5b645b069efee46652da 100644
--- a/src/main/scala/uk/ac/soton/ecs/can/core/ProgramMemory.scala
+++ b/src/main/scala/uk/ac/soton/ecs/can/core/ProgramMemory.scala
@@ -40,9 +40,7 @@ class ProgramMemory(implicit cfg: CanCoreConfiguration) extends MultiIOModule {
 
   cw := mem(pc)
 
-  when(read.en) {
-    read.data := mem(read.addr)
-  }
+  read.data := mem(read.addr)
 
   when(write.en) {
     mem(write.addr) := write.data
diff --git a/src/main/scala/uk/ac/soton/ecs/can/types/MemoryReadIO.scala b/src/main/scala/uk/ac/soton/ecs/can/types/MemoryReadIO.scala
index b0d6f81bc850a73f9cc2ec2b6306376f5e8abfdc..4d16411117648e3d433502702f922d5cda0e88c4 100644
--- a/src/main/scala/uk/ac/soton/ecs/can/types/MemoryReadIO.scala
+++ b/src/main/scala/uk/ac/soton/ecs/can/types/MemoryReadIO.scala
@@ -6,7 +6,6 @@ package uk.ac.soton.ecs.can.types
 import chisel3._
 
 class MemoryReadIO(addrWidth: Int, dataWidth: Int) extends Bundle {
-  val en = Input(Bool())
   val addr = Input(UInt(addrWidth.W))
   val data = Output(UInt(dataWidth.W))
 }