Administrator approval is now required for registering new accounts. If you are registering a new account, and are external to the University, please ask the repository owner to contact ServiceLine to request your account be approved. Repository owners must include the newly registered email address, and specific repository in the request for approval.

Verified Commit 41900e5b authored by Minyong Li's avatar Minyong Li 💬
Browse files

core.{Data,Program}Memory: use dedicated port types

parent 001eaaaf
......@@ -5,21 +5,14 @@ package uk.ac.soton.ecs.can.core
import chisel3._
import chisel3.util.log2Ceil
import uk.ac.soton.ecs.can.types._
import uk.ac.soton.ecs.can.config.CanCoreConfiguration
class DataMemory(implicit cfg: CanCoreConfiguration) extends MultiIOModule {
private val addrWidth = log2Ceil(cfg.dataMemoryWords)
val read = IO(new Bundle {
val en = Input(Bool())
val addr = Input(UInt(addrWidth.W))
val data = Output(UInt(512.W))
})
val write = IO(new Bundle {
val en = Input(Bool())
val addr = Input(UInt(addrWidth.W))
val data = Input(UInt(512.W))
})
val read = IO(new MemoryReadIO(addrWidth, 512))
val write = IO(new MemoryWriteIO(addrWidth, 512))
private val mem =
if (cfg.syncReadMemory)
......
......@@ -5,7 +5,7 @@ package uk.ac.soton.ecs.can.core
import chisel3._
import chisel3.util.log2Ceil
import uk.ac.soton.ecs.can.types.CanCoreControlWord
import uk.ac.soton.ecs.can.types._
import uk.ac.soton.ecs.can.config.CanCoreConfiguration
class ProgramMemory(implicit cfg: CanCoreConfiguration) extends MultiIOModule {
......@@ -19,16 +19,8 @@ class ProgramMemory(implicit cfg: CanCoreConfiguration) extends MultiIOModule {
})
val cw = IO(Output(UInt(cwWidth.W)))
val read = IO(new Bundle {
val en = Input(Bool())
val addr = Input(UInt(addrWidth.W))
val data = Output(UInt(cwWidth.W))
})
val write = IO(new Bundle {
val en = Input(Bool())
val addr = Input(UInt(addrWidth.W))
val data = Input(UInt(cwWidth.W))
})
val read = IO(new MemoryReadIO(addrWidth, cwWidth))
val write = IO(new MemoryWriteIO(addrWidth, cwWidth))
private val mem =
if (cfg.syncReadMemory)
......
// SPDX-FileCopyrightText: 2021 Minyong Li <ml10g20@soton.ac.uk>
// SPDX-License-Identifier: CERN-OHL-W-2.0
package uk.ac.soton.ecs.can.types
import chisel3._
class MemoryReadIO(addrWidth: Int, dataWidth: Int) extends Bundle {
val en = Input(Bool())
val addr = Input(UInt(addrWidth.W))
val data = Output(UInt(dataWidth.W))
}
// SPDX-FileCopyrightText: 2021 Minyong Li <ml10g20@soton.ac.uk>
// SPDX-License-Identifier: CERN-OHL-W-2.0
package uk.ac.soton.ecs.can.types
import chisel3._
class MemoryWriteIO(addrWidth: Int, dataWidth: Int) extends Bundle {
val en = Input(Bool())
val addr = Input(UInt(addrWidth.W))
val data = Input(UInt(dataWidth.W))
}
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment