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Minyong Li
Can
Commits
41900e5b
Verified
Commit
41900e5b
authored
Jul 11, 2021
by
Minyong Li
💬
Browse files
core.{Data,Program}Memory: use dedicated port types
parent
001eaaaf
Changes
4
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Inline
Side-by-side
src/main/scala/uk/ac/soton/ecs/can/core/DataMemory.scala
View file @
41900e5b
...
...
@@ -5,21 +5,14 @@ package uk.ac.soton.ecs.can.core
import
chisel3._
import
chisel3.util.log2Ceil
import
uk.ac.soton.ecs.can.types._
import
uk.ac.soton.ecs.can.config.CanCoreConfiguration
class
DataMemory
(
implicit
cfg
:
CanCoreConfiguration
)
extends
MultiIOModule
{
private
val
addrWidth
=
log2Ceil
(
cfg
.
dataMemoryWords
)
val
read
=
IO
(
new
Bundle
{
val
en
=
Input
(
Bool
())
val
addr
=
Input
(
UInt
(
addrWidth
.
W
))
val
data
=
Output
(
UInt
(
512.
W
))
})
val
write
=
IO
(
new
Bundle
{
val
en
=
Input
(
Bool
())
val
addr
=
Input
(
UInt
(
addrWidth
.
W
))
val
data
=
Input
(
UInt
(
512.
W
))
})
val
read
=
IO
(
new
MemoryReadIO
(
addrWidth
,
512
))
val
write
=
IO
(
new
MemoryWriteIO
(
addrWidth
,
512
))
private
val
mem
=
if
(
cfg
.
syncReadMemory
)
...
...
src/main/scala/uk/ac/soton/ecs/can/core/ProgramMemory.scala
View file @
41900e5b
...
...
@@ -5,7 +5,7 @@ package uk.ac.soton.ecs.can.core
import
chisel3._
import
chisel3.util.log2Ceil
import
uk.ac.soton.ecs.can.types.
CanCoreControlWord
import
uk.ac.soton.ecs.can.types.
_
import
uk.ac.soton.ecs.can.config.CanCoreConfiguration
class
ProgramMemory
(
implicit
cfg
:
CanCoreConfiguration
)
extends
MultiIOModule
{
...
...
@@ -19,16 +19,8 @@ class ProgramMemory(implicit cfg: CanCoreConfiguration) extends MultiIOModule {
})
val
cw
=
IO
(
Output
(
UInt
(
cwWidth
.
W
)))
val
read
=
IO
(
new
Bundle
{
val
en
=
Input
(
Bool
())
val
addr
=
Input
(
UInt
(
addrWidth
.
W
))
val
data
=
Output
(
UInt
(
cwWidth
.
W
))
})
val
write
=
IO
(
new
Bundle
{
val
en
=
Input
(
Bool
())
val
addr
=
Input
(
UInt
(
addrWidth
.
W
))
val
data
=
Input
(
UInt
(
cwWidth
.
W
))
})
val
read
=
IO
(
new
MemoryReadIO
(
addrWidth
,
cwWidth
))
val
write
=
IO
(
new
MemoryWriteIO
(
addrWidth
,
cwWidth
))
private
val
mem
=
if
(
cfg
.
syncReadMemory
)
...
...
src/main/scala/uk/ac/soton/ecs/can/types/MemoryReadIO.scala
0 → 100644
View file @
41900e5b
// SPDX-FileCopyrightText: 2021 Minyong Li <ml10g20@soton.ac.uk>
// SPDX-License-Identifier: CERN-OHL-W-2.0
package
uk.ac.soton.ecs.can.types
import
chisel3._
class
MemoryReadIO
(
addrWidth
:
Int
,
dataWidth
:
Int
)
extends
Bundle
{
val
en
=
Input
(
Bool
())
val
addr
=
Input
(
UInt
(
addrWidth
.
W
))
val
data
=
Output
(
UInt
(
dataWidth
.
W
))
}
src/main/scala/uk/ac/soton/ecs/can/types/MemoryWriteIO.scala
0 → 100644
View file @
41900e5b
// SPDX-FileCopyrightText: 2021 Minyong Li <ml10g20@soton.ac.uk>
// SPDX-License-Identifier: CERN-OHL-W-2.0
package
uk.ac.soton.ecs.can.types
import
chisel3._
class
MemoryWriteIO
(
addrWidth
:
Int
,
dataWidth
:
Int
)
extends
Bundle
{
val
en
=
Input
(
Bool
())
val
addr
=
Input
(
UInt
(
addrWidth
.
W
))
val
data
=
Input
(
UInt
(
dataWidth
.
W
))
}
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