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... as a preparation of architecture refactor.

Architectural change: the flattened columnar round and diagonal
round are now stacked and controlled by a signal, which means only
one can be activated now.

An addition is trivially synthesized to a ripple-carry adder. With
512b + 512b the carry chain is super long and delay becomes super
high. Although the results are same, now just use 16 32b ripple-
carry adders, which is also what the standards specify. Later a
faster adder may be considered.

This commit includes a lot of damages:

- change to a more structural pkg hierarchy: config, core, types
- refactor some modules to use a more OOP paradigm
- further integrate implicit cfg to modules
- add imm width to config
- change all modules to accept UInt, which makes all data paths in
  core UInt(512.W)
- temporary remove all test cases because of the changes above;
  they need to be rewritten
- maybe more

The top level should pass all parameter down.

This is a more Scala-ish and Chisel-ish style for configuring the
core.

Boring change lol

This is the processor without any peripheral.

These are trivial modules, but add convenience when wiring up
the processor.

This will be directly implemented in CanCore instead.

- add a companion object for less verbose cw decl
- add a read port for pm
- test improvements
- naming improvements

A redesign is also performed.

This allows switching between Mem (usually synthesized into
register groups) and SyncReadMem (usually synthesized into FPGA
block memories).

LFSR PRNGs cannot be properly implemented

It turns out that a older version is mistakenly used.