- 11 Jul, 2021 3 commits
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Minyong Li authored
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Minyong Li authored
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Minyong Li authored
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- 08 Jul, 2021 3 commits
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Minyong Li authored
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Minyong Li authored
... as a preparation of architecture refactor.
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Minyong Li authored
Architectural change: the flattened columnar round and diagonal round are now stacked and controlled by a signal, which means only one can be activated now.
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- 07 Jul, 2021 5 commits
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Minyong Li authored
An addition is trivially synthesized to a ripple-carry adder. With 512b + 512b the carry chain is super long and delay becomes super high. Although the results are same, now just use 16 32b ripple- carry adders, which is also what the standards specify. Later a faster adder may be considered.
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Minyong Li authored
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Minyong Li authored
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Minyong Li authored
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Minyong Li authored
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- 06 Jul, 2021 1 commit
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Minyong Li authored
This commit includes a lot of damages: - change to a more structural pkg hierarchy: config, core, types - refactor some modules to use a more OOP paradigm - further integrate implicit cfg to modules - add imm width to config - change all modules to accept UInt, which makes all data paths in core UInt(512.W) - temporary remove all test cases because of the changes above; they need to be rewritten - maybe more
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- 05 Jul, 2021 5 commits
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Minyong Li authored
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Minyong Li authored
The top level should pass all parameter down.
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Minyong Li authored
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Minyong Li authored
This is a more Scala-ish and Chisel-ish style for configuring the core.
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Minyong Li authored
Boring change lol
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- 26 Jun, 2021 7 commits
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Minyong Li authored
This is the processor without any peripheral.
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Minyong Li authored
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Minyong Li authored
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Minyong Li authored
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Minyong Li authored
These are trivial modules, but add convenience when wiring up the processor.
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Minyong Li authored
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Minyong Li authored
This will be directly implemented in CanCore instead.
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- 25 Jun, 2021 4 commits
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Minyong Li authored
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Minyong Li authored
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Minyong Li authored
- add a companion object for less verbose cw decl - add a read port for pm - test improvements - naming improvements
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Minyong Li authored
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- 24 Jun, 2021 5 commits
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Minyong Li authored
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Minyong Li authored
A redesign is also performed.
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Minyong Li authored
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Minyong Li authored
This allows switching between Mem (usually synthesized into register groups) and SyncReadMem (usually synthesized into FPGA block memories).
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Minyong Li authored
LFSR PRNGs cannot be properly implemented
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- 23 Jun, 2021 1 commit
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Minyong Li authored
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- 17 Jun, 2021 2 commits
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Minyong Li authored
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Minyong Li authored
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- 16 Jun, 2021 4 commits
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Minyong Li authored
It turns out that a older version is mistakenly used.
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Minyong Li authored
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Minyong Li authored
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Minyong Li authored
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