Verified Commit 052643e4 authored by Minyong Li's avatar Minyong Li 💬
Browse files

core.DataMemoryTest: remove redundant step cycles

parent 3fb7fb0a
......@@ -19,19 +19,19 @@ class DataMemoryTest extends FlatSpec with ChiselScalatestTester {
c.write.addr.poke("h01".U(addrWidth.W))
c.write.data.poke("h1234".U(dataWidth.W))
c.write.en.poke(true.B)
c.clock.step(2)
c.clock.step()
c.write.en.poke(false.B)
c.read.addr.poke("h01".U(addrWidth.W))
c.clock.step(2)
c.clock.step()
c.read.data.expect("h1234".U(dataWidth.W))
c.write.addr.poke("h0a".U(addrWidth.W))
c.write.data.poke("hfefe".U(dataWidth.W))
c.write.en.poke(true.B)
c.clock.step(2)
c.clock.step()
c.write.en.poke(false.B)
c.read.addr.poke("h0a".U(addrWidth.W))
c.clock.step(2)
c.clock.step()
c.read.data.expect("hfefe".U(dataWidth.W))
}
}
......@@ -41,14 +41,14 @@ class DataMemoryTest extends FlatSpec with ChiselScalatestTester {
c.write.addr.poke("h06".U(addrWidth.W))
c.write.data.poke("hcafe".U(dataWidth.W))
c.write.en.poke(true.B)
c.clock.step(2)
c.clock.step()
c.write.en.poke(false.B)
c.read.addr.poke("h06".U(addrWidth.W))
c.clock.step(2)
c.clock.step()
c.read.data.expect("hcafe".U(dataWidth.W))
c.write.data.poke("hefac".U(dataWidth.W))
c.clock.step(8)
c.clock.step()
c.read.data.expect("hcafe".U(dataWidth.W))
}
}
......
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