From 052643e4b3fddeb151315eff02f2d382d8f3f9cb Mon Sep 17 00:00:00 2001
From: Minyong Li <ml10g20@soton.ac.uk>
Date: Thu, 24 Jun 2021 20:42:46 +0100
Subject: [PATCH] core.DataMemoryTest: remove redundant step cycles
---
.../uk/ac/soton/ecs/can/core/DataMemoryTest.scala | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/src/test/scala/uk/ac/soton/ecs/can/core/DataMemoryTest.scala b/src/test/scala/uk/ac/soton/ecs/can/core/DataMemoryTest.scala
index 088cf53..936cff0 100644
--- a/src/test/scala/uk/ac/soton/ecs/can/core/DataMemoryTest.scala
+++ b/src/test/scala/uk/ac/soton/ecs/can/core/DataMemoryTest.scala
@@ -19,19 +19,19 @@ class DataMemoryTest extends FlatSpec with ChiselScalatestTester {
c.write.addr.poke("h01".U(addrWidth.W))
c.write.data.poke("h1234".U(dataWidth.W))
c.write.en.poke(true.B)
- c.clock.step(2)
+ c.clock.step()
c.write.en.poke(false.B)
c.read.addr.poke("h01".U(addrWidth.W))
- c.clock.step(2)
+ c.clock.step()
c.read.data.expect("h1234".U(dataWidth.W))
c.write.addr.poke("h0a".U(addrWidth.W))
c.write.data.poke("hfefe".U(dataWidth.W))
c.write.en.poke(true.B)
- c.clock.step(2)
+ c.clock.step()
c.write.en.poke(false.B)
c.read.addr.poke("h0a".U(addrWidth.W))
- c.clock.step(2)
+ c.clock.step()
c.read.data.expect("hfefe".U(dataWidth.W))
}
}
@@ -41,14 +41,14 @@ class DataMemoryTest extends FlatSpec with ChiselScalatestTester {
c.write.addr.poke("h06".U(addrWidth.W))
c.write.data.poke("hcafe".U(dataWidth.W))
c.write.en.poke(true.B)
- c.clock.step(2)
+ c.clock.step()
c.write.en.poke(false.B)
c.read.addr.poke("h06".U(addrWidth.W))
- c.clock.step(2)
+ c.clock.step()
c.read.data.expect("hcafe".U(dataWidth.W))
c.write.data.poke("hefac".U(dataWidth.W))
- c.clock.step(8)
+ c.clock.step()
c.read.data.expect("hcafe".U(dataWidth.W))
}
}
--
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