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Verified Commit 1c7fc06b authored by Minyong Li's avatar Minyong Li 💬
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core.ChaChaRound: impl, substitude core.*Round

parent 3fcce836
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...@@ -11,8 +11,8 @@ class ChaChaBlock(val regBetweenRounds: Boolean = true) extends MultiIOModule { ...@@ -11,8 +11,8 @@ class ChaChaBlock(val regBetweenRounds: Boolean = true) extends MultiIOModule {
val in = IO(Input(Vec(16, UInt(32.W)))) val in = IO(Input(Vec(16, UInt(32.W))))
val out = IO(Output(Vec(16, UInt(32.W)))) val out = IO(Output(Vec(16, UInt(32.W))))
private val columnRound = Module(new ColumnRound) private val columnRound = Module(ChaChaRound.columnar)
private val diagonalRound = Module(new DiagonalRound) private val diagonalRound = Module(ChaChaRound.diagonal)
private val betweenRounds = private val betweenRounds =
if (regBetweenRounds) Reg(Vec(16, UInt(32.W))) if (regBetweenRounds) Reg(Vec(16, UInt(32.W)))
else Wire(Vec(16, UInt(32.W))) else Wire(Vec(16, UInt(32.W)))
......
...@@ -5,20 +5,36 @@ package uk.ac.soton.ecs.can.core ...@@ -5,20 +5,36 @@ package uk.ac.soton.ecs.can.core
import chisel3._ import chisel3._
class ColumnRound extends MultiIOModule { class ChaChaRound(wires: Seq[Seq[Int]]) extends MultiIOModule {
val in = IO(Input(Vec(16, UInt(32.W)))) val in = IO(Input(Vec(16, UInt(32.W))))
val out = IO(Output(Vec(16, UInt(32.W)))) val out = IO(Output(Vec(16, UInt(32.W))))
wires.foreach { qRWires =>
val quarterRound = Module(new QuarterRound)
qRWires.zipWithIndex.foreach { case (qRWire, index) =>
quarterRound.in(index) := in(qRWire)
out(qRWire) := quarterRound.out(index)
}
}
}
object ChaChaRound {
def columnar = new ChaChaRound(
Seq( Seq(
Seq(0, 4, 8, 12), Seq(0, 4, 8, 12),
Seq(1, 5, 9, 13), Seq(1, 5, 9, 13),
Seq(2, 6, 10, 14), Seq(2, 6, 10, 14),
Seq(3, 7, 11, 15) Seq(3, 7, 11, 15)
).foreach { roundWires => )
val quarterRound = Module(new QuarterRound) )
roundWires.zipWithIndex.foreach { roundWire =>
quarterRound.in(roundWire._2) := in(roundWire._1) def diagonal = new ChaChaRound(
out(roundWire._1) := quarterRound.out(roundWire._2) Seq(
} Seq(0, 5, 10, 15),
} Seq(1, 6, 11, 12),
Seq(2, 7, 8, 13),
Seq(3, 4, 9, 14)
)
)
} }
// SPDX-FileCopyrightText: 2021 Minyong Li <ml10g20@soton.ac.uk>
// SPDX-License-Identifier: CERN-OHL-W-2.0
package uk.ac.soton.ecs.can.core
import chisel3._
class DiagonalRound extends MultiIOModule {
val in = IO(Input(Vec(16, UInt(32.W))))
val out = IO(Output(Vec(16, UInt(32.W))))
Seq(
Seq(0, 5, 10, 15),
Seq(1, 6, 11, 12),
Seq(2, 7, 8, 13),
Seq(3, 4, 9, 14)
).foreach { roundWires =>
val quarterRound = Module(new QuarterRound)
roundWires.zipWithIndex.foreach { roundWire =>
quarterRound.in(roundWire._2) := in(roundWire._1)
out(roundWire._1) := quarterRound.out(roundWire._2)
}
}
}
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