core.ChaChaRound: impl, substitude core.*Round

src/main/scala/uk/ac/soton/ecs/can/core/ChaChaBlock.scala

@@ -11,8 +11,8 @@ class ChaChaBlock(val regBetweenRounds: Boolean = true) extends MultiIOModule {
   val in = IO(Input(Vec(16, UInt(32.W))))
   val out = IO(Output(Vec(16, UInt(32.W))))
 
-  private val columnRound = Module(new ColumnRound)
-  private val diagonalRound = Module(new DiagonalRound)
+  private val columnRound = Module(ChaChaRound.columnar)
+  private val diagonalRound = Module(ChaChaRound.diagonal)
   private val betweenRounds =
     if (regBetweenRounds) Reg(Vec(16, UInt(32.W)))
     else Wire(Vec(16, UInt(32.W)))

src/main/scala/uk/ac/soton/ecs/can/core/ColumnRound.scala → src/main/scala/uk/ac/soton/ecs/can/core/ChaChaRound.scala

@@ -5,20 +5,36 @@ package uk.ac.soton.ecs.can.core
 
 import chisel3._
 
-class ColumnRound extends MultiIOModule {
+class ChaChaRound(wires: Seq[Seq[Int]]) extends MultiIOModule {
   val in = IO(Input(Vec(16, UInt(32.W))))
   val out = IO(Output(Vec(16, UInt(32.W))))
 
-  Seq(
-    Seq(0, 4, 8, 12),
-    Seq(1, 5, 9, 13),
-    Seq(2, 6, 10, 14),
-    Seq(3, 7, 11, 15)
-  ).foreach { roundWires =>
+  wires.foreach { qRWires =>
     val quarterRound = Module(new QuarterRound)
-    roundWires.zipWithIndex.foreach { roundWire =>
-      quarterRound.in(roundWire._2) := in(roundWire._1)
-      out(roundWire._1) := quarterRound.out(roundWire._2)
+
+    qRWires.zipWithIndex.foreach { case (qRWire, index) =>
+      quarterRound.in(index) := in(qRWire)
+      out(qRWire) := quarterRound.out(index)
     }
   }
 }
+
+object ChaChaRound {
+  def columnar = new ChaChaRound(
+    Seq(
+      Seq(0, 4, 8, 12),
+      Seq(1, 5, 9, 13),
+      Seq(2, 6, 10, 14),
+      Seq(3, 7, 11, 15)
+    )
+  )
+
+  def diagonal = new ChaChaRound(
+    Seq(
+      Seq(0, 5, 10, 15),
+      Seq(1, 6, 11, 12),
+      Seq(2, 7, 8, 13),
+      Seq(3, 4, 9, 14)
+    )
+  )
+}

src/main/scala/uk/ac/soton/ecs/can/core/DiagonalRound.scala

-// SPDX-FileCopyrightText: 2021 Minyong Li <ml10g20@soton.ac.uk>
-// SPDX-License-Identifier: CERN-OHL-W-2.0
-
-package uk.ac.soton.ecs.can.core
-
-import chisel3._
-
-class DiagonalRound extends MultiIOModule {
-  val in = IO(Input(Vec(16, UInt(32.W))))
-  val out = IO(Output(Vec(16, UInt(32.W))))
-
-  Seq(
-    Seq(0, 5, 10, 15),
-    Seq(1, 6, 11, 12),
-    Seq(2, 7, 8, 13),
-    Seq(3, 4, 9, 14)
-  ).foreach { roundWires =>
-    val quarterRound = Module(new QuarterRound)
-    roundWires.zipWithIndex.foreach { roundWire =>
-      quarterRound.in(roundWire._2) := in(roundWire._1)
-      out(roundWire._1) := quarterRound.out(roundWire._2)
-    }
-  }
-}