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Created with Raphaël 2.2.06Sep29Aug23222122Jul131211876527Jun262524231716151413108717May1618Marfpga/de1-soc/CanCore.qsf: updatemainmain.gitignore: add .qwstestbench/CanCore.tb.v: add reset and delays before $stopfirmware/test: fix wrong hex cwRevert "core.*Memory: add mem load for simulation"0.1.00.1.0firmware/test: add program and data for demofpga/de1-soc/CanCore.qsf: update project settingsfpga/de1-soc/CanCore.sdc: comment out io constraints.gitignore: add nativelink log filetestbench/CanCore.tb.v: add testbench for CanCoreutil/chacha20.c: add software impl for debugging.gitignore: update to ignore binary filescore.BlockFunctionTest: addcore.RoundTest: addcore.BaseRound: fix reversed castscore.BaseQuarterRound: use better methodscore.QuarterRoundTest: fix comb test vector usecore.*Memory: add mem load for simulation.gitignore: add *.ffpga/de1-soc: add Quartus Prime project file w/ constraint.gitignore: add moreMain: add main entrycore.CanCore: add IO bundle types and use themCanConfiguration: removecore.CanCore: add halted output signalcore: remove branching supportcore.{Data,Program}Memory: fix Read-After-Write behaviortypes.CanCoreALUFunction: add license headercore.ALU: add bypass funcscore.Round: removecore.ProgramMemory: fix 2-readcore.CanCore: re-impl, refactorMemoryReadIO: remove read enablecore.{Data,Program}Memory: use dedicated port typescore.ALU: add, w/ CW changescore.{Data,Program}Memory: add read enable signalcore.DataMemory: change ports from 2r1w to 1r1wcore.CanCore: temporarily remove all the codecore.Round: add a grouped round blockcore.Adder: fix timing by using Z_{2^{32}} arithmetics