From 41900e5b9caad3b944469498e7db9b69224eaaf5 Mon Sep 17 00:00:00 2001
From: Minyong Li <ml10g20@soton.ac.uk>
Date: Sun, 11 Jul 2021 14:26:42 +0100
Subject: [PATCH] core.{Data,Program}Memory: use dedicated port types
---
.../uk/ac/soton/ecs/can/core/DataMemory.scala | 13 +++----------
.../uk/ac/soton/ecs/can/core/ProgramMemory.scala | 14 +++-----------
.../uk/ac/soton/ecs/can/types/MemoryReadIO.scala | 12 ++++++++++++
.../uk/ac/soton/ecs/can/types/MemoryWriteIO.scala | 12 ++++++++++++
4 files changed, 30 insertions(+), 21 deletions(-)
create mode 100644 src/main/scala/uk/ac/soton/ecs/can/types/MemoryReadIO.scala
create mode 100644 src/main/scala/uk/ac/soton/ecs/can/types/MemoryWriteIO.scala
diff --git a/src/main/scala/uk/ac/soton/ecs/can/core/DataMemory.scala b/src/main/scala/uk/ac/soton/ecs/can/core/DataMemory.scala
index 0dfeb68..074a29a 100644
--- a/src/main/scala/uk/ac/soton/ecs/can/core/DataMemory.scala
+++ b/src/main/scala/uk/ac/soton/ecs/can/core/DataMemory.scala
@@ -5,21 +5,14 @@ package uk.ac.soton.ecs.can.core
import chisel3._
import chisel3.util.log2Ceil
+import uk.ac.soton.ecs.can.types._
import uk.ac.soton.ecs.can.config.CanCoreConfiguration
class DataMemory(implicit cfg: CanCoreConfiguration) extends MultiIOModule {
private val addrWidth = log2Ceil(cfg.dataMemoryWords)
- val read = IO(new Bundle {
- val en = Input(Bool())
- val addr = Input(UInt(addrWidth.W))
- val data = Output(UInt(512.W))
- })
- val write = IO(new Bundle {
- val en = Input(Bool())
- val addr = Input(UInt(addrWidth.W))
- val data = Input(UInt(512.W))
- })
+ val read = IO(new MemoryReadIO(addrWidth, 512))
+ val write = IO(new MemoryWriteIO(addrWidth, 512))
private val mem =
if (cfg.syncReadMemory)
diff --git a/src/main/scala/uk/ac/soton/ecs/can/core/ProgramMemory.scala b/src/main/scala/uk/ac/soton/ecs/can/core/ProgramMemory.scala
index a65cd41..ca27c96 100644
--- a/src/main/scala/uk/ac/soton/ecs/can/core/ProgramMemory.scala
+++ b/src/main/scala/uk/ac/soton/ecs/can/core/ProgramMemory.scala
@@ -5,7 +5,7 @@ package uk.ac.soton.ecs.can.core
import chisel3._
import chisel3.util.log2Ceil
-import uk.ac.soton.ecs.can.types.CanCoreControlWord
+import uk.ac.soton.ecs.can.types._
import uk.ac.soton.ecs.can.config.CanCoreConfiguration
class ProgramMemory(implicit cfg: CanCoreConfiguration) extends MultiIOModule {
@@ -19,16 +19,8 @@ class ProgramMemory(implicit cfg: CanCoreConfiguration) extends MultiIOModule {
})
val cw = IO(Output(UInt(cwWidth.W)))
- val read = IO(new Bundle {
- val en = Input(Bool())
- val addr = Input(UInt(addrWidth.W))
- val data = Output(UInt(cwWidth.W))
- })
- val write = IO(new Bundle {
- val en = Input(Bool())
- val addr = Input(UInt(addrWidth.W))
- val data = Input(UInt(cwWidth.W))
- })
+ val read = IO(new MemoryReadIO(addrWidth, cwWidth))
+ val write = IO(new MemoryWriteIO(addrWidth, cwWidth))
private val mem =
if (cfg.syncReadMemory)
diff --git a/src/main/scala/uk/ac/soton/ecs/can/types/MemoryReadIO.scala b/src/main/scala/uk/ac/soton/ecs/can/types/MemoryReadIO.scala
new file mode 100644
index 0000000..b0d6f81
--- /dev/null
+++ b/src/main/scala/uk/ac/soton/ecs/can/types/MemoryReadIO.scala
@@ -0,0 +1,12 @@
+// SPDX-FileCopyrightText: 2021 Minyong Li <ml10g20@soton.ac.uk>
+// SPDX-License-Identifier: CERN-OHL-W-2.0
+
+package uk.ac.soton.ecs.can.types
+
+import chisel3._
+
+class MemoryReadIO(addrWidth: Int, dataWidth: Int) extends Bundle {
+ val en = Input(Bool())
+ val addr = Input(UInt(addrWidth.W))
+ val data = Output(UInt(dataWidth.W))
+}
diff --git a/src/main/scala/uk/ac/soton/ecs/can/types/MemoryWriteIO.scala b/src/main/scala/uk/ac/soton/ecs/can/types/MemoryWriteIO.scala
new file mode 100644
index 0000000..438ccb1
--- /dev/null
+++ b/src/main/scala/uk/ac/soton/ecs/can/types/MemoryWriteIO.scala
@@ -0,0 +1,12 @@
+// SPDX-FileCopyrightText: 2021 Minyong Li <ml10g20@soton.ac.uk>
+// SPDX-License-Identifier: CERN-OHL-W-2.0
+
+package uk.ac.soton.ecs.can.types
+
+import chisel3._
+
+class MemoryWriteIO(addrWidth: Int, dataWidth: Int) extends Bundle {
+ val en = Input(Bool())
+ val addr = Input(UInt(addrWidth.W))
+ val data = Input(UInt(dataWidth.W))
+}
--
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