core.ProgramMemory: fix 2-read

Two simultaneous read causes Quartus to synthesize additional BRAM
and is unnecessary. This commit attempts to make Quartus to infer
a Simple Dual-Port RAM.

Plus a take pin exposed from CanCore, which can be used to take
control on both of the memories.

src/main/scala/uk/ac/soton/ecs/can/core/CanCore.scala

@@ -20,6 +20,7 @@ class CanCore(implicit cfg: CanCoreConfiguration) extends MultiIOModule {
   //////////////////// Ports ////////////////////
 
   val io = IO(new Bundle {
+    val take = Input(Bool())
     val programMemory = new Bundle {
       val read =
         new MemoryReadIO(programMemoryAddressWidth, programMemoryDataWidth)
@@ -27,7 +28,6 @@ class CanCore(implicit cfg: CanCoreConfiguration) extends MultiIOModule {
         new MemoryWriteIO(programMemoryAddressWidth, programMemoryDataWidth)
     }
     val dataMemory = new Bundle {
-      val take = Input(Bool())
       val read =
         new MemoryReadIO(dataMemoryAddressWidth, dataMemoryDataWidth)
       val write =
@@ -44,24 +44,25 @@ class CanCore(implicit cfg: CanCoreConfiguration) extends MultiIOModule {
 
   //////////////////// Control Paths ////////////////////
 
-  private val ctrl = programMemory.cw.asTypeOf(new CanCoreControlWord)
+  private val ctrl = programMemory.read.data.asTypeOf(new CanCoreControlWord)
 
   programMemory.br.abs := ctrl.absoluteBranch
   programMemory.br.rel := ctrl.relativeBranch
   programMemory.br.addr := ctrl.immediate
+  programMemory.take := io.take
 
   dataMemory.read.addr := Mux(
-    io.dataMemory.take,
+    io.take,
     io.dataMemory.read.addr,
     ctrl.dataMemoryReadAddress
   )
   dataMemory.write.en := Mux(
-    io.dataMemory.take,
+    io.take,
     io.dataMemory.write.en,
     ctrl.dataMemoryWriteEnable
   )
   dataMemory.write.addr := Mux(
-    io.dataMemory.take,
+    io.take,
     io.dataMemory.write.addr,
     ctrl.dataMemoryWriteAddress
   )
@@ -83,7 +84,7 @@ class CanCore(implicit cfg: CanCoreConfiguration) extends MultiIOModule {
 
   io.dataMemory.read.data := dataMemory.read.data
   dataMemory.write.data := Mux(
-    io.dataMemory.take,
+    io.take,
     io.dataMemory.write.data,
     alu.y
   )

src/main/scala/uk/ac/soton/ecs/can/core/ProgramMemory.scala

@@ -4,7 +4,7 @@
 package uk.ac.soton.ecs.can.core
 
 import chisel3._
-import chisel3.util.log2Ceil
+import chisel3.util.{MuxLookup, log2Ceil}
 import uk.ac.soton.ecs.can.types._
 import uk.ac.soton.ecs.can.config.CanCoreConfiguration
 
@@ -17,7 +17,7 @@ class ProgramMemory(implicit cfg: CanCoreConfiguration) extends MultiIOModule {
     val rel = Input(Bool())
     val addr = Input(UInt(addrWidth.W))
   })
-  val cw = IO(Output(UInt(cwWidth.W)))
+  val take = IO(Input(Bool()))
 
   val read = IO(new MemoryReadIO(addrWidth, cwWidth))
   val write = IO(new MemoryWriteIO(addrWidth, cwWidth))
@@ -30,17 +30,21 @@ class ProgramMemory(implicit cfg: CanCoreConfiguration) extends MultiIOModule {
 
   private val pc = RegInit(0.U(addrWidth.W))
 
-  when(br.abs) {
-    pc := br.addr.asUInt()
-  }.elsewhen(br.rel) {
-    pc := (pc.asSInt() + br.addr.asSInt()).asUInt()
-  }.otherwise {
-    pc := pc + 1.U
-  }
-
-  cw := mem(pc)
-
-  read.data := mem(read.addr)
+  pc := Mux(
+    take,
+    pc,
+    Mux(
+      br.abs,
+      br.addr.asUInt(),
+      Mux(
+        br.rel,
+        (pc.asSInt() + br.addr.asSInt()).asUInt(),
+        pc + 1.U
+      )
+    )
+  )
+
+  read.data := mem(Mux(take, read.addr, pc))
 
   when(write.en) {
     mem(write.addr) := write.data