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Verified Commit ac7c2585 authored by Minyong Li's avatar Minyong Li 💬
Browse files

Revert "core.*Memory: add mem load for simulation"

91d71c41 already includes the memory load instructions. In addition,
these bind statements do not work well with a few tools I use.

This reverts commit d7827bd8.
parent 9e63e4d7
Pipeline #7481 passed with stage
in 56 seconds
......@@ -5,7 +5,6 @@ package uk.ac.soton.ecs.can.core
import chisel3._
import chisel3.util.log2Ceil
import chisel3.util.experimental.loadMemoryFromFile
import uk.ac.soton.ecs.can.types._
import uk.ac.soton.ecs.can.config.CanCoreConfiguration
......@@ -26,6 +25,4 @@ class DataMemory(implicit cfg: CanCoreConfiguration) extends MultiIOModule {
when(write.en) {
mem(write.addr) := write.data
}
loadMemoryFromFile(mem, "firmware/test/test.data.hex")
}
......@@ -5,7 +5,6 @@ package uk.ac.soton.ecs.can.core
import chisel3._
import chisel3.util.log2Ceil
import chisel3.util.experimental.loadMemoryFromFile
import uk.ac.soton.ecs.can.config.CanCoreConfiguration
import uk.ac.soton.ecs.can.types._
......@@ -37,6 +36,4 @@ class ProgramMemory(implicit cfg: CanCoreConfiguration) extends MultiIOModule {
when(write.en) {
mem(write.addr) := write.data
}
loadMemoryFromFile(mem, "firmware/test/test.prog.hex")
}
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