Revert "core.*Memory: add mem load for simulation"

91d71c41 already includes the memory load instructions. In addition,
these bind statements do not work well with a few tools I use.

This reverts commit d7827bd8.

src/main/scala/uk/ac/soton/ecs/can/core/DataMemory.scala

@@ -5,7 +5,6 @@ package uk.ac.soton.ecs.can.core
 
 import chisel3._
 import chisel3.util.log2Ceil
-import chisel3.util.experimental.loadMemoryFromFile
 import uk.ac.soton.ecs.can.types._
 import uk.ac.soton.ecs.can.config.CanCoreConfiguration
 
@@ -26,6 +25,4 @@ class DataMemory(implicit cfg: CanCoreConfiguration) extends MultiIOModule {
   when(write.en) {
     mem(write.addr) := write.data
   }
-
-  loadMemoryFromFile(mem, "firmware/test/test.data.hex")
 }

src/main/scala/uk/ac/soton/ecs/can/core/ProgramMemory.scala

@@ -5,7 +5,6 @@ package uk.ac.soton.ecs.can.core
 
 import chisel3._
 import chisel3.util.log2Ceil
-import chisel3.util.experimental.loadMemoryFromFile
 import uk.ac.soton.ecs.can.config.CanCoreConfiguration
 import uk.ac.soton.ecs.can.types._
 
@@ -37,6 +36,4 @@ class ProgramMemory(implicit cfg: CanCoreConfiguration) extends MultiIOModule {
   when(write.en) {
     mem(write.addr) := write.data
   }
-
-  loadMemoryFromFile(mem, "firmware/test/test.prog.hex")
 }