Verified Commit d7827bd8 authored by Minyong Li's avatar Minyong Li 💬
Browse files

core.*Memory: add mem load for simulation

parent b57e4b57
......@@ -5,6 +5,7 @@ package uk.ac.soton.ecs.can.core
import chisel3._
import chisel3.util.log2Ceil
import chisel3.util.experimental.loadMemoryFromFile
import uk.ac.soton.ecs.can.types._
import uk.ac.soton.ecs.can.config.CanCoreConfiguration
......@@ -25,4 +26,6 @@ class DataMemory(implicit cfg: CanCoreConfiguration) extends MultiIOModule {
when(write.en) {
mem(write.addr) := write.data
}
loadMemoryFromFile(mem, "firmware/test/test.data.hex")
}
......@@ -5,6 +5,7 @@ package uk.ac.soton.ecs.can.core
import chisel3._
import chisel3.util.log2Ceil
import chisel3.util.experimental.loadMemoryFromFile
import uk.ac.soton.ecs.can.config.CanCoreConfiguration
import uk.ac.soton.ecs.can.types._
......@@ -36,4 +37,6 @@ class ProgramMemory(implicit cfg: CanCoreConfiguration) extends MultiIOModule {
when(write.en) {
mem(write.addr) := write.data
}
loadMemoryFromFile(mem, "firmware/test/test.prog.hex")
}
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