From d7827bd842f8af06065e5c100186c8b4bdc9604b Mon Sep 17 00:00:00 2001
From: Minyong Li <ml10g20@soton.ac.uk>
Date: Sat, 21 Aug 2021 14:31:31 +0100
Subject: [PATCH] core.*Memory: add mem load for simulation

---
 src/main/scala/uk/ac/soton/ecs/can/core/DataMemory.scala    | 3 +++
 src/main/scala/uk/ac/soton/ecs/can/core/ProgramMemory.scala | 3 +++
 2 files changed, 6 insertions(+)

diff --git a/src/main/scala/uk/ac/soton/ecs/can/core/DataMemory.scala b/src/main/scala/uk/ac/soton/ecs/can/core/DataMemory.scala
index e4a1f78..7feb2a8 100644
--- a/src/main/scala/uk/ac/soton/ecs/can/core/DataMemory.scala
+++ b/src/main/scala/uk/ac/soton/ecs/can/core/DataMemory.scala
@@ -5,6 +5,7 @@ package uk.ac.soton.ecs.can.core
 
 import chisel3._
 import chisel3.util.log2Ceil
+import chisel3.util.experimental.loadMemoryFromFile
 import uk.ac.soton.ecs.can.types._
 import uk.ac.soton.ecs.can.config.CanCoreConfiguration
 
@@ -25,4 +26,6 @@ class DataMemory(implicit cfg: CanCoreConfiguration) extends MultiIOModule {
   when(write.en) {
     mem(write.addr) := write.data
   }
+
+  loadMemoryFromFile(mem, "firmware/test/test.data.hex")
 }
diff --git a/src/main/scala/uk/ac/soton/ecs/can/core/ProgramMemory.scala b/src/main/scala/uk/ac/soton/ecs/can/core/ProgramMemory.scala
index 5cc4271..572eb07 100644
--- a/src/main/scala/uk/ac/soton/ecs/can/core/ProgramMemory.scala
+++ b/src/main/scala/uk/ac/soton/ecs/can/core/ProgramMemory.scala
@@ -5,6 +5,7 @@ package uk.ac.soton.ecs.can.core
 
 import chisel3._
 import chisel3.util.log2Ceil
+import chisel3.util.experimental.loadMemoryFromFile
 import uk.ac.soton.ecs.can.config.CanCoreConfiguration
 import uk.ac.soton.ecs.can.types._
 
@@ -36,4 +37,6 @@ class ProgramMemory(implicit cfg: CanCoreConfiguration) extends MultiIOModule {
   when(write.en) {
     mem(write.addr) := write.data
   }
+
+  loadMemoryFromFile(mem, "firmware/test/test.prog.hex")
 }
-- 
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