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Minyong Li
Can
Commits
cfedc8ce
Verified
Commit
cfedc8ce
authored
Sep 06, 2021
by
Minyong Li
💬
Browse files
testbench/CanCore.tb.v: add reset and delays before $stop
This stops at the middle of memory write back.
parent
fb03c4c0
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testbench/CanCore.tb.v
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@@ -44,7 +44,10 @@ initial begin
$
readmemh
(
"../../../../firmware/test/test.prog.hex"
,
canCore
.
programMemory
.
mem
);
$
readmemh
(
"../../../../firmware/test/test.data.hex"
,
canCore
.
dataMemory
.
mem
);
$
stop
;
#
2
reset
<=
0
;
// Refer to test.prog.hex for the number of steps
#
59
$
stop
;
end
endmodule
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