From cfedc8ceeed629f93ac6ee08b5642dd9db4dbdec Mon Sep 17 00:00:00 2001
From: Minyong Li <ml10g20@soton.ac.uk>
Date: Mon, 6 Sep 2021 12:16:31 +0100
Subject: [PATCH] testbench/CanCore.tb.v: add reset and delays before $stop
This stops at the middle of memory write back.
---
testbench/CanCore.tb.v | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/testbench/CanCore.tb.v b/testbench/CanCore.tb.v
index 6174d5f..5553e11 100644
--- a/testbench/CanCore.tb.v
+++ b/testbench/CanCore.tb.v
@@ -44,7 +44,10 @@ initial begin
$readmemh("../../../../firmware/test/test.prog.hex", canCore.programMemory.mem);
$readmemh("../../../../firmware/test/test.data.hex", canCore.dataMemory.mem);
- $stop;
+ #2 reset <= 0;
+
+ // Refer to test.prog.hex for the number of steps
+ #59 $stop;
end
endmodule
--
GitLab