Skip to content
GitLab
Explore
Sign in
Register
Primary navigation
Search or go to…
Project
C
Can
Manage
Activity
Members
Labels
Plan
Issues
Issue boards
Milestones
Wiki
Code
Merge requests
Repository
Branches
Commits
Tags
Repository graph
Compare revisions
Snippets
Build
Pipelines
Jobs
Pipeline schedules
Artifacts
Deploy
Releases
Package registry
Model registry
Operate
Environments
Terraform modules
Monitor
Incidents
Analyze
Value stream analytics
Contributor analytics
CI/CD analytics
Repository analytics
Model experiments
Help
Help
Support
GitLab documentation
Compare GitLab plans
GitLab community forum
Contribute to GitLab
Provide feedback
Keyboard shortcuts
?
Snippets
Groups
Projects
Show more breadcrumbs
Minyong Li
Can
Commits
80312628
Verified
Commit
80312628
authored
3 years ago
by
Minyong Li
Browse files
Options
Downloads
Patches
Plain Diff
fpga/de1-soc/CanCore.qsf: update project settings
parent
94cd5de7
No related branches found
No related tags found
No related merge requests found
Changes
1
Show whitespace changes
Inline
Side-by-side
Showing
1 changed file
fpga/de1-soc/CanCore.qsf
+7
-1
7 additions, 1 deletion
fpga/de1-soc/CanCore.qsf
with
7 additions
and
1 deletion
fpga/de1-soc/CanCore.qsf
+
7
−
1
View file @
80312628
...
@@ -75,4 +75,10 @@ set_instance_assignment -name VIRTUAL_PIN ON -to io_programMemory_write_data
...
@@ -75,4 +75,10 @@ set_instance_assignment -name VIRTUAL_PIN ON -to io_programMemory_write_data
set_location_assignment PIN_AF14 -to clock
set_location_assignment PIN_AF14 -to clock
set_global_assignment -name SDC_FILE CanCore.sdc
set_global_assignment -name SDC_FILE CanCore.sdc
set_global_assignment -name VERILOG_FILE ../../CanCore.v
set_global_assignment -name VERILOG_FILE ../../CanCore.v
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH CanCoreTest -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_NAME CanCoreTest -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id CanCoreTest
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME CanCoreTest -section_id CanCoreTest
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name EDA_TEST_BENCH_FILE ../../testbench/CanCore.tb.v -section_id CanCoreTest
\ No newline at end of file
This diff is collapsed.
Click to expand it.
Preview
0%
Loading
Try again
or
attach a new file
.
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Save comment
Cancel
Please
register
or
sign in
to comment