fpga/de1-soc/CanCore.sdc: comment out io constraints

fpga/de1-soc/CanCore.sdc

@@ -3,4 +3,6 @@
 # SPDX-License-Identifier: CC0-1.0
 
 create_clock -name CLK_50MHz -period 20 [get_ports {clock}]
-set_false_path -from [get_ports {io_*}] -to [get_ports {io_*}]
+
+# IO ports are currently set to virtual pins and cannot be constrained
+# set_false_path -from [get_ports {io_*}] -to [get_ports {io_*}]