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Verified Commit 1b84b48a authored by Minyong Li's avatar Minyong Li 💬
Browse files

Main: add main entry

parent 5a7a9f52
// SPDX-FileCopyrightText: 2021 Minyong Li <>
// SPDX-License-Identifier: GPL-3.0-or-later
import chisel3.stage._
import chisel3.util.log2Ceil
object Main extends App {
implicit private val coreCfg = CanCoreConfiguration(
immediateWidth = log2Ceil(128),
programMemoryWords = 128,
dataMemoryWords = 16,
syncReadMemory = true,
registerFileWords = 2,
quarterRoundType = 1
private val stage = new ChiselStage
Seq(ChiselGeneratorAnnotation(() => new CanCore))
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