Verified Commit 5a7a9f52 authored by Minyong Li's avatar Minyong Li 💬
Browse files

core.CanCore: add IO bundle types and use them

parent 488e2597
......@@ -19,23 +19,14 @@ class CanCore(implicit cfg: CanCoreConfiguration) extends MultiIOModule {
//////////////////// Ports ////////////////////
val io = IO(new Bundle {
val take = Input(Bool())
val halted = Output(Bool())
val programMemory = new Bundle {
val read =
new MemoryReadIO(programMemoryAddressWidth, programMemoryDataWidth)
val write =
new MemoryWriteIO(programMemoryAddressWidth, programMemoryDataWidth)
}
val dataMemory = new Bundle {
val read =
new MemoryReadIO(dataMemoryAddressWidth, dataMemoryDataWidth)
val write =
new MemoryWriteIO(dataMemoryAddressWidth, dataMemoryDataWidth)
}
})
val io = IO(
new CanCoreIO(
programMemoryAddressWidth,
programMemoryDataWidth,
dataMemoryAddressWidth,
dataMemoryDataWidth
)
)
//////////////////// Modules ////////////////////
......
// SPDX-FileCopyrightText: 2021 Minyong Li <ml10g20@soton.ac.uk>
// SPDX-License-Identifier: CERN-OHL-W-2.0
package uk.ac.soton.ecs.can.types
import chisel3._
class CanCoreIO(
programMemoryAddressWidth: Int,
programMemoryDataWidth: Int,
dataMemoryAddressWidth: Int,
dataMemoryDataWidth: Int
) extends Bundle {
val take = Input(Bool())
val halted = Output(Bool())
val programMemory =
new MemoryReadWriteIO(programMemoryAddressWidth, programMemoryDataWidth)
val dataMemory =
new MemoryReadWriteIO(dataMemoryAddressWidth, dataMemoryDataWidth)
}
// SPDX-FileCopyrightText: 2021 Minyong Li <ml10g20@soton.ac.uk>
// SPDX-License-Identifier: CERN-OHL-W-2.0
package uk.ac.soton.ecs.can.types
import chisel3._
class MemoryReadWriteIO(
addrWidth: Int,
dataWidth: Int
) extends Bundle {
val read = new MemoryReadIO(addrWidth, dataWidth)
val write = new MemoryWriteIO(addrWidth, dataWidth)
}
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