core: remove branching support

There is now only a 'halt' signal that stops the processor.

src/main/scala/uk/ac/soton/ecs/can/core/CanCore.scala

@@ -46,10 +46,7 @@ class CanCore(implicit cfg: CanCoreConfiguration) extends MultiIOModule {
 
   private val ctrl = programMemory.read.data.asTypeOf(new CanCoreControlWord)
 
-  programMemory.br.abs := ctrl.absoluteBranch
-  programMemory.br.rel := ctrl.relativeBranch
-  programMemory.br.addr := ctrl.immediate
-  programMemory.take := io.take
+  programMemory.halt := Mux(io.take, io.take, ctrl.halt)
 
   dataMemory.read.addr := Mux(
     io.take,

src/main/scala/uk/ac/soton/ecs/can/core/ProgramMemory.scala

@@ -12,12 +12,7 @@ class ProgramMemory(implicit cfg: CanCoreConfiguration) extends MultiIOModule {
   private val addrWidth = log2Ceil(cfg.programMemoryWords)
   private val cwWidth = (new CanCoreControlWord).getWidth
 
-  val br = IO(new Bundle {
-    val abs = Input(Bool())
-    val rel = Input(Bool())
-    val addr = Input(UInt(addrWidth.W))
-  })
-  val take = IO(Input(Bool()))
+  val halt = IO(Input(Bool()))
 
   val read = IO(new MemoryReadIO(addrWidth, cwWidth))
   val write = IO(new MemoryWriteIO(addrWidth, cwWidth))
@@ -34,21 +29,9 @@ class ProgramMemory(implicit cfg: CanCoreConfiguration) extends MultiIOModule {
 
   private val pc = RegInit(0.U(addrWidth.W))
 
-  pc := Mux(
-    take,
-    pc,
-    Mux(
-      br.abs,
-      br.addr.asUInt(),
-      Mux(
-        br.rel,
-        (pc.asSInt() + br.addr.asSInt()).asUInt(),
-        pc + 1.U
-      )
-    )
-  )
+  pc := Mux(halt, pc, pc + 1.U)
 
-  read.data := mem(Mux(take, read.addr, pc))
+  read.data := mem(Mux(halt, read.addr, pc))
 
   when(write.en) {
     mem(write.addr) := write.data

src/main/scala/uk/ac/soton/ecs/can/types/CanCoreControlWord.scala

@@ -12,9 +12,7 @@ class CanCoreControlWord(implicit val cfg: CanCoreConfiguration)
   private val dataMemoryAddressWidth = log2Ceil(cfg.dataMemoryWords)
   private val registerFileAddressWidth = log2Ceil(cfg.registerFileWords)
 
-  val immediate = UInt(cfg.immediateWidth.W)
-  val absoluteBranch = Bool()
-  val relativeBranch = Bool()
+  val halt = Bool()
 
   val dataMemoryReadAddress = UInt(dataMemoryAddressWidth.W)
   val dataMemoryWriteEnable = Bool()