From 2b87115fee9d3e53279b55040b51885d867c19d4 Mon Sep 17 00:00:00 2001
From: Minyong Li <ml10g20@soton.ac.uk>
Date: Thu, 22 Jul 2021 15:56:49 +0100
Subject: [PATCH] core: remove branching support
There is now only a 'halt' signal that stops the processor.
---
.../uk/ac/soton/ecs/can/core/CanCore.scala | 5 +---
.../ac/soton/ecs/can/core/ProgramMemory.scala | 23 +++----------------
.../ecs/can/types/CanCoreControlWord.scala | 4 +---
3 files changed, 5 insertions(+), 27 deletions(-)
diff --git a/src/main/scala/uk/ac/soton/ecs/can/core/CanCore.scala b/src/main/scala/uk/ac/soton/ecs/can/core/CanCore.scala
index 1e9ee71..6da5138 100644
--- a/src/main/scala/uk/ac/soton/ecs/can/core/CanCore.scala
+++ b/src/main/scala/uk/ac/soton/ecs/can/core/CanCore.scala
@@ -46,10 +46,7 @@ class CanCore(implicit cfg: CanCoreConfiguration) extends MultiIOModule {
private val ctrl = programMemory.read.data.asTypeOf(new CanCoreControlWord)
- programMemory.br.abs := ctrl.absoluteBranch
- programMemory.br.rel := ctrl.relativeBranch
- programMemory.br.addr := ctrl.immediate
- programMemory.take := io.take
+ programMemory.halt := Mux(io.take, io.take, ctrl.halt)
dataMemory.read.addr := Mux(
io.take,
diff --git a/src/main/scala/uk/ac/soton/ecs/can/core/ProgramMemory.scala b/src/main/scala/uk/ac/soton/ecs/can/core/ProgramMemory.scala
index 1f96ea5..5cc4271 100644
--- a/src/main/scala/uk/ac/soton/ecs/can/core/ProgramMemory.scala
+++ b/src/main/scala/uk/ac/soton/ecs/can/core/ProgramMemory.scala
@@ -12,12 +12,7 @@ class ProgramMemory(implicit cfg: CanCoreConfiguration) extends MultiIOModule {
private val addrWidth = log2Ceil(cfg.programMemoryWords)
private val cwWidth = (new CanCoreControlWord).getWidth
- val br = IO(new Bundle {
- val abs = Input(Bool())
- val rel = Input(Bool())
- val addr = Input(UInt(addrWidth.W))
- })
- val take = IO(Input(Bool()))
+ val halt = IO(Input(Bool()))
val read = IO(new MemoryReadIO(addrWidth, cwWidth))
val write = IO(new MemoryWriteIO(addrWidth, cwWidth))
@@ -34,21 +29,9 @@ class ProgramMemory(implicit cfg: CanCoreConfiguration) extends MultiIOModule {
private val pc = RegInit(0.U(addrWidth.W))
- pc := Mux(
- take,
- pc,
- Mux(
- br.abs,
- br.addr.asUInt(),
- Mux(
- br.rel,
- (pc.asSInt() + br.addr.asSInt()).asUInt(),
- pc + 1.U
- )
- )
- )
+ pc := Mux(halt, pc, pc + 1.U)
- read.data := mem(Mux(take, read.addr, pc))
+ read.data := mem(Mux(halt, read.addr, pc))
when(write.en) {
mem(write.addr) := write.data
diff --git a/src/main/scala/uk/ac/soton/ecs/can/types/CanCoreControlWord.scala b/src/main/scala/uk/ac/soton/ecs/can/types/CanCoreControlWord.scala
index 0ccc8e5..d6845a5 100644
--- a/src/main/scala/uk/ac/soton/ecs/can/types/CanCoreControlWord.scala
+++ b/src/main/scala/uk/ac/soton/ecs/can/types/CanCoreControlWord.scala
@@ -12,9 +12,7 @@ class CanCoreControlWord(implicit val cfg: CanCoreConfiguration)
private val dataMemoryAddressWidth = log2Ceil(cfg.dataMemoryWords)
private val registerFileAddressWidth = log2Ceil(cfg.registerFileWords)
- val immediate = UInt(cfg.immediateWidth.W)
- val absoluteBranch = Bool()
- val relativeBranch = Bool()
+ val halt = Bool()
val dataMemoryReadAddress = UInt(dataMemoryAddressWidth.W)
val dataMemoryWriteEnable = Bool()
--
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