Commits · main · SoCLabs / SRAM Chiplet

Jan 16, 2025
- Update ASIC flow and Gate level sims · 38ddfa8c
  Daniel Newbrook authored 2 months ago
  
  38ddfa8c
Nov 06, 2024
- Increase AXI ID width to 12 · a772308d
  Daniel Newbrook authored 5 months ago
  
  a772308d
Sep 10, 2024
- Update ASIC flow, make SRAM 1MB, add clocks for asynchronous interfaces · 4e9b15be
  Daniel Newbrook authored 7 months ago
  
  4e9b15be
Sep 03, 2024
- Initial Add slim 16k SRAM · 80706779
  Daniel Newbrook authored 7 months ago
  
  80706779
- Add VDD and VSS width for standard cells · 0394a503
  Daniel Newbrook authored 7 months ago
  
  0394a503
- Update ASIC flow · 9a979d59
  Daniel Newbrook authored 7 months ago
  
  9a979d59
- Add Synopsys IP and ASIC flow for Fusion Compiler · 8fda30ef
  Daniel Newbrook authored 7 months ago
  
  8fda30ef
Aug 29, 2024
- Cleanup simulation flow and Add start of ASIC flow · 38032868
  Daniel Newbrook authored 7 months ago
  
  38032868
Aug 27, 2024
- Fixed nic400_tlx missing microarchitecture · 9f4efa46
  Daniel Newbrook authored 7 months ago
  
  9f4efa46
- Update readme to with run instructions · 613e4af2
  Daniel Newbrook authored 7 months ago
  
  613e4af2
- Add default SIE300 path · 73e8ef70
  Daniel Newbrook authored 7 months ago
  
  73e8ef70
- Update address ranges and fix byte writes and reads · 79ab6f6a
  Daniel Newbrook authored 7 months ago
  
  79ab6f6a
Aug 21, 2024
- TLX + SRAM working - no FT1248 yet · 82790d6f
  Daniel Newbrook authored 7 months ago
  
  82790d6f
Aug 19, 2024
- intial project structure · 813ea974
  Daniel Newbrook authored 7 months ago
  
  813ea974
- Add gitignore and makefile · a00bc688
  Daniel Newbrook authored 7 months ago
  
  a00bc688
- Initial commit · 6694b41d
  dwn1c21 authored 7 months ago
  
  6694b41d