38ddfa8c · Update ASIC flow and Gate level sims

a772308d · Increase AXI ID width to 12

4e9b15be · Update ASIC flow, make SRAM 1MB, add clocks for asynchronous interf...

80706779 · Initial Add slim 16k SRAM

0394a503 · Add VDD and VSS width for standard cells

9a979d59 · Update ASIC flow

8fda30ef · Add Synopsys IP and ASIC flow for Fusion Compiler

38032868 · Cleanup simulation flow and Add start of ASIC flow

9f4efa46 · Fixed nic400_tlx missing microarchitecture

613e4af2 · Update readme to with run instructions

73e8ef70 · Add default SIE300 path

79ab6f6a · Update address ranges and fix byte writes and reads

82790d6f · TLX + SRAM working - no FT1248 yet

813ea974 · intial project structure

a00bc688 · Add gitignore and makefile