Add VDD and VSS width for standard cells

ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/power_plan.tcl

@@ -5,7 +5,7 @@ create_pg_ring_pattern ring_pattern -horizontal_layer M7 -horizontal_width {5} -
 
 create_pg_mesh_pattern mesh_pattern -layers {{{vertical_layer: M8} {width: 1} {pitch: 30} {offset: 20}} \
                                                 {{horizontal_layer: M5} {width: 1} {pitch: 30} {offset: 20}}}
-create_pg_std_cell_conn_pattern std_pattern -layers M1 
+create_pg_std_cell_conn_pattern std_pattern -layers {M1} -check_std_cell_drc false -mark_as_follow_pin false -rail_width {0.13 0.13}
 
 set_pg_strategy core_ring -pattern {{name: ring_pattern} {nets: {VDD VSS}} {offset: {3 3}}} -core 
 set_pg_strategy M5M8_mesh -pattern {{name: mesh_pattern} {nets: {VDD VSS}}} -core