From 0394a50352c9bf4f3605c5136ed13be282e32c5e Mon Sep 17 00:00:00 2001
From: Daniel Newbrook <dwn1c21@soton.ac.uk>
Date: Tue, 3 Sep 2024 15:37:21 +0100
Subject: [PATCH] Add VDD and VSS width for standard cells
---
ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/power_plan.tcl | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/power_plan.tcl b/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/power_plan.tcl
index 7800b24..407e63e 100644
--- a/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/power_plan.tcl
+++ b/ASIC/TSMC28nm_HPCP/Synopsys_FC_flow/power_plan.tcl
@@ -5,7 +5,7 @@ create_pg_ring_pattern ring_pattern -horizontal_layer M7 -horizontal_width {5} -
create_pg_mesh_pattern mesh_pattern -layers {{{vertical_layer: M8} {width: 1} {pitch: 30} {offset: 20}} \
{{horizontal_layer: M5} {width: 1} {pitch: 30} {offset: 20}}}
-create_pg_std_cell_conn_pattern std_pattern -layers M1
+create_pg_std_cell_conn_pattern std_pattern -layers {M1} -check_std_cell_drc false -mark_as_follow_pin false -rail_width {0.13 0.13}
set_pg_strategy core_ring -pattern {{name: ring_pattern} {nets: {VDD VSS}} {offset: {3 3}}} -core
set_pg_strategy M5M8_mesh -pattern {{name: mesh_pattern} {nets: {VDD VSS}}} -core
--
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