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Commit 813ea974 authored by Daniel Newbrook's avatar Daniel Newbrook
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intial project structure

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.gitignore
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View file @ 813ea974
./logical/nic400_sram_chiplet
./logical/nic400_tlx_sram_chiplet
\ No newline at end of file
.project
.ecmproject
logical/nic400_sram_chiplet/
logical/nic400_tlx_sram_chiplet/
logical/SMC
logical/shared
simulate
verif/cocotb/sim_build
verif/cocotb/__pycache__
verif/cocotb/*.vstf
verif/cocotb/*.wlf
verif/cocotb/transcript
verif/cocotb/results.xml
verif/cocotb/*.ini
imp
logical/SRAM/verilog/SRAM_wrapper.v 0 → 100644
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logical/top_sram_chiplet/verilog/top_sram_chiplet.v 0 → 100644
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make.cfg 0 → 100644
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SIE300_IP_LOGICAL_DIR:=
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socrates/BP301_SRAM/config/SRAM_ctrl.yaml 0 → 100644
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#----------------------------------------------------------------------------
# The confidential and proprietary information contained in this file may
# only be used by a person authorised under and to the extent permitted
# by a subsisting licensing agreement from Arm Limited or its affiliates.
#
# (C) COPYRIGHT 2019 Arm Limited or its affiliates.
# ALL RIGHTS RESERVED
#
# This entire notice must be reproduced on all copies of this file
# and copies of this file may only be made by a person if such person is
# permitted to do so under the terms of a subsisting license agreement
# from Arm Limited or its affiliates.
#----------------------------------------------------------------------------
#
# Version Information
#
# Checked In : Mon Jul 15 17:15:15 2019 +0100
#
# Revision : 828f11fd
#
# Release Information : CoreLink SIE-300 Generic Global Bundle r1p2-00rel0
#
#----------------------------------------------------------------------------
# Abstract : Configuration file for SIE-300 AXI5 SRAM Controller
#----------------------------------------------------------------------------
# -----------------------------
# User Configuration
# -----------------------------
#
# COMPONENT: Name of the component to configure.
# Valid values:
# [sie300_axi5_sram_ctrl]
#
COMPONENT: sie300_axi5_sram_ctrl
#
# CONFIG_NAME: Name of the configuration.
# Each unifiqued element and top is suffixed with
# _${CONFIG_NAME}
#
CONFIG_NAME: sram_chiplet
#
# ADDR_WIDTH: AXI5 Address Bus width
# Valid values:
# 14-24
ADDR_WIDTH: 21
#
# DATA_WIDTH: AXI5 Data Bus width
# Valid values:
# [32,64,128,256]
DATA_WIDTH: 32
#
# ID_WIDTH: AXI5 ID width for all channels
# Valid values:
# 2-32
ID_WIDTH: 4
#
# QCLK_SYNC_EN: Add 2 DFF synchronizer on inputs of clock Q-channel
# Valid values:
# - 0 : no synchronizer
# - 1 : added synchronizer
QCLK_SYNC_EN: 1
#
# QPWR_SYNC_EN: Add 2 DFF synchronizer on inputs of power Q-channel
# Valid values:
# - 0 : no synchronizer
# - 1 : added synchronizer
QPWR_SYNC_EN: 1
#
# QEXT_SYNC_EN: Add 2 DFF synchronizer on inputs of external gating Q-channel
# Valid values:
# - 0 : no synchronizer
# - 1 : added synchronizer
QEXT_SYNC_EN: 1
#
# EXCLUSIVE_MONITORS: Number of Exclusive Access Monitors to observe
# and track AXI locked transactions
# Valid values:
# 0-16 (0 means no locked transaction support)
EXCLUSIVE_MONITORS: 2
#
# AR_BUF_SIZE: Size of FIFO on AR channel
# Valid values:
# 1-16
AR_BUF_SIZE: 4
#
# AW_BUF_SIZE: Size of FIFO on AW channel
# Valid values:
# 1-16
AW_BUF_SIZE: 4
#
# W_BUF_SIZE: Size of FIFO on W channel
# Valid values:
# 1-16
W_BUF_SIZE: 8
#
# REGISTER_AXI_AR: Enables / disables register stage at the AR FIFO
# Valid values:
# [BYPASS,FULL]
REGISTER_AXI_AR: BYPASS
#
# REGISTER_AXI_R: Enables / disables register stage at the R FIFO
# Valid values:
# [BYPASS,FULL]
REGISTER_AXI_R: BYPASS
#
# AXI5_POISON_EN: Enables / disables AXI5 Data Poisoning support
# Valid values:
# [0,1]
AXI5_POISON_EN: 0
socrates/nic400_sram_chiplet/nic400_sram_chiplet.xml 0 → 100644
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socrates/nic400_tb/nic400_tb.xml 0 → 100644
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<?xml version="1.0" encoding="UTF-8"?>
<ConfiguredComponent>
<Name>nic400_tb</Name>
<Suffix>tb</Suffix>
<ConfigurableComponentRef>
<Vendor>arm.com</Vendor>
<Library>CoreLink</Library>
<Name>nic400</Name>
<Version>r1p2</Version>
</ConfigurableComponentRef>
<Specification>
<Parameters>
<AWUSERWidth>0</AWUSERWidth>
<ARUSERWidth>0</ARUSERWidth>
<WUSERWidth>0</WUSERWidth>
<BUSERWidth>0</BUSERWidth>
<RUSERWidth>0</RUSERWidth>
<GlobalIDWidth>0</GlobalIDWidth>
<HierarchicalClockGating>false</HierarchicalClockGating>
<ClockControllerImplementation>asynchronous</ClockControllerImplementation>
<RSBCentralRing>false</RSBCentralRing>
<DefaultProtocol>axi4</DefaultProtocol>
<UppercaseRTLSignals>true</UppercaseRTLSignals>
<Taxonomy>master_slave</Taxonomy>
<QoSEnabled>false</QoSEnabled>
<QVNEnabled>false</QVNEnabled>
</Parameters>
<Domains>
<VoltageDomains>
<VoltageDomain>
<Name>vd0</Name>
</VoltageDomain>
</VoltageDomains>
<PowerDomains>
<PowerDomain>
<Name>pd0</Name>
<PowerDomainType>AlwaysOn</PowerDomainType>
<VoltageDomainRef>vd0</VoltageDomainRef>
</PowerDomain>
</PowerDomains>
<ClockDomains>
<ClockDomain>
<Name>clk0</Name>
<ClockDomainType>physical</ClockDomainType>
<PowerDomainRef>pd0</PowerDomainRef>
</ClockDomain>
</ClockDomains>
<ClockRelations/>
</Domains>
<Groups>
<ExternalGroups/>
<APBGroups/>
</Groups>
<Interfaces/>
<MemoryMaps>
</MemoryMaps>
<Paths/>
<VirtualNetworks/>
</Specification>
<Architecture/>
<Deliverables>
<IPXACT/>
<RTL/>
<TestBench/>
<Reports/>
</Deliverables>
</ConfiguredComponent>
\ No newline at end of file
socrates/nic400_tlx_sram_chiplet/nic400_tlx_sram_chiplet.xml 0 → 100644
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<?xml version="1.0" encoding="UTF-8"?>
<ConfiguredComponent>
<Name>nic400_tlx_sram_chiplet</Name>
<Suffix>sram_chiplet</Suffix>
<ConfigurableComponentRef>
<Vendor>arm.com</Vendor>
<Library>CoreLink</Library>
<Name>nic400_tlx</Name>
<Version>r1p2</Version>
</ConfigurableComponentRef>
<Specification>
<Parameters>
<ARUSERWidth>0</ARUSERWidth>
<AWUSERWidth>0</AWUSERWidth>
<RUSERWidth>0</RUSERWidth>
<WUSERWidth>0</WUSERWidth>
<BUSERWidth>0</BUSERWidth>
<IDWidth>4</IDWidth>
<AddressWidth>32</AddressWidth>
<SlaveDataWidth>32</SlaveDataWidth>
<MasterDataWidth>32</MasterDataWidth>
<SlaveReadAcceptance>16</SlaveReadAcceptance>
<SlaveWriteAcceptance>16</SlaveWriteAcceptance>
<MasterReadIssuing>16</MasterReadIssuing>
<MasterWriteIssuing>16</MasterWriteIssuing>
<MasterTotalIssuing>16</MasterTotalIssuing>
<MultiRegion>false</MultiRegion>
<LockSupport>false</LockSupport>
<SLAVE_PROTOCOL>AXI</SLAVE_PROTOCOL>
<MASTER_PROTOCOL>AXI</MASTER_PROTOCOL>
<EarlyWriteResponse>true</EarlyWriteResponse>
<AllowBrokenBurst>false</AllowBrokenBurst>
<SLAVE_CLOCK>clk_s</SLAVE_CLOCK>
<MASTER_CLOCK>clk_m</MASTER_CLOCK>
<FW_USER_DEFINED_WIDTH>8</FW_USER_DEFINED_WIDTH>
<FW_PACKING_STRATEGY>widest_div_4</FW_PACKING_STRATEGY>
<FW_TLX_TIMING_CLOSURE>false</FW_TLX_TIMING_CLOSURE>
<REV_PACKING_STRATEGY>widest_div_4</REV_PACKING_STRATEGY>
<REV_USER_DEFINED_WIDTH>8</REV_USER_DEFINED_WIDTH>
<REV_TLX_TIMING_CLOSURE>false</REV_TLX_TIMING_CLOSURE>
<AWSlavePortRegister>present</AWSlavePortRegister>
<AWSlavePortRegisterType>rev</AWSlavePortRegisterType>
<AWMasterPortRegister>absent</AWMasterPortRegister>
<AWMasterPortRegisterType>fwd</AWMasterPortRegisterType>
<AWBoundaryBuffering>absent</AWBoundaryBuffering>
<AWBoundaryBufferingDepth>2</AWBoundaryBufferingDepth>
<AWCreditBuffers>6</AWCreditBuffers>
<ARSlavePortRegister>present</ARSlavePortRegister>
<ARSlavePortRegisterType>rev</ARSlavePortRegisterType>
<ARMasterPortRegister>absent</ARMasterPortRegister>
<ARMasterPortRegisterType>fwd</ARMasterPortRegisterType>
<ARBoundaryBuffering>absent</ARBoundaryBuffering>
<ARBoundaryBufferingDepth>2</ARBoundaryBufferingDepth>
<ARCreditBuffers>6</ARCreditBuffers>
<WSlavePortRegister>present</WSlavePortRegister>
<WSlavePortRegisterType>rev</WSlavePortRegisterType>
<WMasterPortRegister>absent</WMasterPortRegister>
<WMasterPortRegisterType>fwd</WMasterPortRegisterType>
<WBoundaryBuffering>absent</WBoundaryBuffering>
<WBoundaryBufferingDepth>2</WBoundaryBufferingDepth>
<WCreditBuffers>6</WCreditBuffers>
<RSlavePortRegister>absent</RSlavePortRegister>
<RSlavePortRegisterType>fwd</RSlavePortRegisterType>
<RMasterPortRegister>absent</RMasterPortRegister>
<RMasterPortRegisterType>fwd</RMasterPortRegisterType>
<RBoundaryBuffering>absent</RBoundaryBuffering>
<RBoundaryBufferingDepth>2</RBoundaryBufferingDepth>
<RCreditBuffers>6</RCreditBuffers>
<BSlavePortRegister>absent</BSlavePortRegister>
<BSlavePortRegisterType>fwd</BSlavePortRegisterType>
<BMasterPortRegister>absent</BMasterPortRegister>
<BMasterPortRegisterType>fwd</BMasterPortRegisterType>
<BBoundaryBuffering>absent</BBoundaryBuffering>
<BBoundaryBufferingDepth>2</BBoundaryBufferingDepth>
<BCreditBuffers>6</BCreditBuffers>
<ASlavePortRegister>absent</ASlavePortRegister>
<ASlavePortRegisterType>fwd</ASlavePortRegisterType>
<AMasterPortRegister>absent</AMasterPortRegister>
<AMasterPortRegisterType>fwd</AMasterPortRegisterType>
<ABoundaryBuffering>absent</ABoundaryBuffering>
<ABoundaryBufferingDepth>2</ABoundaryBufferingDepth>
<ACreditBuffers>6</ACreditBuffers>
<DSlavePortRegister>absent</DSlavePortRegister>
<DSlavePortRegisterType>fwd</DSlavePortRegisterType>
<DMasterPortRegister>absent</DMasterPortRegister>
<DMasterPortRegisterType>fwd</DMasterPortRegisterType>
<DBoundaryBuffering>absent</DBoundaryBuffering>
<DBoundaryBufferingDepth>2</DBoundaryBufferingDepth>
<DCreditBuffers>6</DCreditBuffers>
<FwdChannelPLRegisterSlices>0</FwdChannelPLRegisterSlices>
<RevChannelPLRegisterSlices>0</RevChannelPLRegisterSlices>
<POWER_DOMAIN_CROSSING>false</POWER_DOMAIN_CROSSING>
<HierarchicalClockGating>false</HierarchicalClockGating>
<ClockControllerImplementation>asynchronous</ClockControllerImplementation>
<QoSEnabled>false</QoSEnabled>
<OutputSignals>false</OutputSignals>
<QVNEnabled>false</QVNEnabled>
<VNExternal>false</VNExternal>
<VNExternalBridge>false</VNExternalBridge>
<MASTER_PREALLOC_1>false</MASTER_PREALLOC_1>
<MASTER_PREALLOC_2>false</MASTER_PREALLOC_2>
<MASTER_PREALLOC_3>false</MASTER_PREALLOC_3>
<MASTER_PREALLOC_4>false</MASTER_PREALLOC_4>
<SLAVE_PREALLOC_1>false</SLAVE_PREALLOC_1>
<SLAVE_PREALLOC_2>false</SLAVE_PREALLOC_2>
<SLAVE_PREALLOC_3>false</SLAVE_PREALLOC_3>
<SLAVE_PREALLOC_4>false</SLAVE_PREALLOC_4>
<FW_PHYSICAL_LINK>16</FW_PHYSICAL_LINK>
<REV_PHYSICAL_LINK>16</REV_PHYSICAL_LINK>
<FW_AXI_SIGNAL>145</FW_AXI_SIGNAL>
<REV_AXI_SIGNAL>45</REV_AXI_SIGNAL>
<FW_BANDWIDTH_PERCENTAGE>17</FW_BANDWIDTH_PERCENTAGE>
<FW_UTILIZATION_PERCENTAGE>86</FW_UTILIZATION_PERCENTAGE>
<FW_REDUCTION_PERCENTAGE>91</FW_REDUCTION_PERCENTAGE>
<REV_BANDWIDTH_PERCENTAGE>24</REV_BANDWIDTH_PERCENTAGE>
<REV_UTILIZATION_PERCENTAGE>98</REV_UTILIZATION_PERCENTAGE>
<REV_REDUCTION_PERCENTAGE>78</REV_REDUCTION_PERCENTAGE>
<DPEEnabled>false</DPEEnabled>
<ParityBitWidth>5</ParityBitWidth>
</Parameters>
<Domains>
<VoltageDomains>
<VoltageDomain>
<Name>vd0</Name>
</VoltageDomain>
</VoltageDomains>
<PowerDomains>
<PowerDomain>
<Name>pd0</Name>
<PowerDomainType>AlwaysOn</PowerDomainType>
<VoltageDomainRef>vd0</VoltageDomainRef>
</PowerDomain>
</PowerDomains>
<ClockDomains>
<ClockDomain>
<Name>clk_s</Name>
<PowerDomainRef>pd0</PowerDomainRef>
</ClockDomain>
<ClockDomain>
<Name>clk_m</Name>
<PowerDomainRef>pd0</PowerDomainRef>
</ClockDomain>
</ClockDomains>
<ClockRelations/>
<GeographicDomains>
<GeographicDomain>
<Name>gd0</Name>
</GeographicDomain>
<GeographicDomain>
<Name>gd1</Name>
</GeographicDomain>
</GeographicDomains>
</Domains>
<Groups>
<ExternalGroups/>
</Groups>
<Interfaces>
<SlaveInterface>
<Name>M1_s</Name>
<AXISlaveProtocol>
<AddressWidth>32</AddressWidth>
<DataWidth>32</DataWidth>
<ARUSEREnabled>false</ARUSEREnabled>
<AWUSEREnabled>false</AWUSEREnabled>
<RUSEREnabled>false</RUSEREnabled>
<WUSEREnabled>false</WUSEREnabled>
<BUSEREnabled>false</BUSEREnabled>
</AXISlaveProtocol>
<ClockRef>clk_s</ClockRef>
</SlaveInterface>
<MasterInterface>
<Name>M1_m</Name>
<AXIMasterProtocol>
<AddressWidth>32</AddressWidth>
<DataWidth>32</DataWidth>
<ARUSEREnabled>false</ARUSEREnabled>
<AWUSEREnabled>false</AWUSEREnabled>
<RUSEREnabled>false</RUSEREnabled>
<WUSEREnabled>false</WUSEREnabled>
<BUSEREnabled>false</BUSEREnabled>
</AXIMasterProtocol>
<ClockRef>clk_m</ClockRef>
</MasterInterface>
</Interfaces>
<MemoryMaps>
<MemoryMap>
<Name>mm0</Name>
<MemoryMapSource>
<InterfaceRef>M1_s</InterfaceRef>
</MemoryMapSource>
<MappedBlock>
<InterfaceRef>M1_m</InterfaceRef>
<Offset>0</Offset>
<Range>4000000000000</Range>
</MappedBlock>
</MemoryMap>
</MemoryMaps>
<Paths>
<Path>
<Source>
<InterfaceRef>M1_s</InterfaceRef>
</Source>
<Targets>
<Target>
<InterfaceRef>M1_m</InterfaceRef>
</Target>
</Targets>
</Path>
</Paths>
<VirtualNetworks/>
</Specification>
<Architecture>
<NICConfigFile>&lt;?xml version=&quot;1.0&quot; encoding=&quot;iso-8859-1&quot; ?&gt;
&lt;periph&gt;
&lt;product_version_info major_version=&quot;00&quot; minor_revision=&quot;2&quot; major_revision=&quot;1&quot; minor_version=&quot;0&quot; part_quality=&quot;rel&quot; minor_code=&quot;50000&quot; major_group=&quot;bu&quot; product_code=&quot;nic400_tlx&quot;/&gt;
&lt;validator_version_info minor_revision=&quot;1&quot; major_revision=&quot;22&quot; /&gt;
&lt;global&gt;
&lt;qos_status&gt;false&lt;/qos_status&gt;
&lt;buser_width&gt;0&lt;/buser_width&gt;
&lt;hcg_en&gt;false&lt;/hcg_en&gt;
&lt;virtual_networks_status&gt;false&lt;/virtual_networks_status&gt;
&lt;rsb_arch_central_ring&gt;false&lt;/rsb_arch_central_ring&gt;
&lt;thin_links_status&gt;true&lt;/thin_links_status&gt;
&lt;awuser_width&gt;0&lt;/awuser_width&gt;
&lt;license_status&gt;unlicensed_nic&lt;/license_status&gt;
&lt;dpe_status&gt;false&lt;/dpe_status&gt;
&lt;aruser_width&gt;0&lt;/aruser_width&gt;
&lt;cc_type&gt;async&lt;/cc_type&gt;
&lt;pl_id_width&gt;4&lt;/pl_id_width&gt;
&lt;ruser_width&gt;0&lt;/ruser_width&gt;
&lt;wuser_width&gt;0&lt;/wuser_width&gt;
&lt;/global&gt;
&lt;amib&gt;
&lt;master_if_port_name&gt;M1_m_m&lt;/master_if_port_name&gt;
&lt;multi_region&gt;false&lt;/multi_region&gt;
&lt;tide&gt;0&lt;/tide&gt;
&lt;tlx&gt;
&lt;power_domain_crossing&gt;false&lt;/power_domain_crossing&gt;
&lt;fwd_tlx&gt;
&lt;pl_clock_ratio&gt;1&lt;/pl_clock_ratio&gt;
&lt;dll_link_user_def_width&gt;8&lt;/dll_link_user_def_width&gt;
&lt;pl_reg_stages&gt;0&lt;/pl_reg_stages&gt;
&lt;dll_link_width_option&gt;widest_div_4&lt;/dll_link_width_option&gt;
&lt;/fwd_tlx&gt;
&lt;rev_tlx&gt;
&lt;pl_clock_ratio&gt;1&lt;/pl_clock_ratio&gt;
&lt;dll_link_user_def_width&gt;8&lt;/dll_link_user_def_width&gt;
&lt;pl_reg_stages&gt;0&lt;/pl_reg_stages&gt;
&lt;dll_link_width_option&gt;widest_div_4&lt;/dll_link_width_option&gt;
&lt;/rev_tlx&gt;
&lt;tlx_enable&gt;true&lt;/tlx_enable&gt;
&lt;ahb_bridge&gt;false&lt;/ahb_bridge&gt;
&lt;reg&gt;
&lt;type&gt;fifo&lt;/type&gt;
&lt;impl&gt;present&lt;/impl&gt;
&lt;depth&gt;6&lt;/depth&gt;
&lt;name&gt;aw&lt;/name&gt;
&lt;location&gt;boundary&lt;/location&gt;
&lt;/reg&gt;
&lt;reg&gt;
&lt;type&gt;fifo&lt;/type&gt;
&lt;impl&gt;present&lt;/impl&gt;
&lt;depth&gt;6&lt;/depth&gt;
&lt;name&gt;w&lt;/name&gt;
&lt;location&gt;boundary&lt;/location&gt;
&lt;/reg&gt;
&lt;reg&gt;
&lt;type&gt;fifo&lt;/type&gt;
&lt;impl&gt;present&lt;/impl&gt;
&lt;depth&gt;6&lt;/depth&gt;
&lt;name&gt;b&lt;/name&gt;
&lt;location&gt;boundary&lt;/location&gt;
&lt;/reg&gt;
&lt;reg&gt;
&lt;type&gt;fifo&lt;/type&gt;
&lt;impl&gt;present&lt;/impl&gt;
&lt;depth&gt;6&lt;/depth&gt;
&lt;name&gt;ar&lt;/name&gt;
&lt;location&gt;boundary&lt;/location&gt;
&lt;/reg&gt;
&lt;reg&gt;
&lt;type&gt;fifo&lt;/type&gt;
&lt;impl&gt;present&lt;/impl&gt;
&lt;depth&gt;6&lt;/depth&gt;
&lt;name&gt;r&lt;/name&gt;
&lt;location&gt;boundary&lt;/location&gt;
&lt;/reg&gt;
&lt;reg&gt;
&lt;type&gt;fwd&lt;/type&gt;
&lt;impl&gt;absent&lt;/impl&gt;
&lt;name&gt;d&lt;/name&gt;
&lt;location&gt;tlx_fwd&lt;/location&gt;
&lt;/reg&gt;
&lt;reg&gt;
&lt;type&gt;fwd&lt;/type&gt;
&lt;impl&gt;absent&lt;/impl&gt;
&lt;name&gt;d&lt;/name&gt;
&lt;location&gt;tlx_rev&lt;/location&gt;
&lt;/reg&gt;
&lt;/tlx&gt;
&lt;slave_if_data_width&gt;32&lt;/slave_if_data_width&gt;
&lt;multi_ported&gt;false&lt;/multi_ported&gt;
&lt;vn_external&gt;none&lt;/vn_external&gt;
&lt;vid_width&gt;4&lt;/vid_width&gt;
&lt;apb_config&gt;false&lt;/apb_config&gt;
&lt;qv_out&gt;false&lt;/qv_out&gt;
&lt;master_if_addr_width&gt;32&lt;/master_if_addr_width&gt;
&lt;clock_domain_name_slave_if&gt;clk_s&lt;/clock_domain_name_slave_if&gt;
&lt;clock_domain_name_master_if&gt;clk_m&lt;/clock_domain_name_master_if&gt;
&lt;protocol&gt;axi&lt;/protocol&gt;
&lt;dest_type&gt;peripheral&lt;/dest_type&gt;
&lt;name&gt;M1_m&lt;/name&gt;
&lt;vn_external_bridge&gt;none&lt;/vn_external_bridge&gt;
&lt;trustzone&gt;nsec&lt;/trustzone&gt;
&lt;slave_if_port_name&gt;M1_m_s&lt;/slave_if_port_name&gt;
&lt;clock_boundary&gt;async&lt;/clock_boundary&gt;
&lt;master_if_data_width&gt;32&lt;/master_if_data_width&gt;
&lt;reg&gt;
&lt;type&gt;rev&lt;/type&gt;
&lt;impl&gt;present&lt;/impl&gt;
&lt;name&gt;aw&lt;/name&gt;
&lt;location&gt;slave_port&lt;/location&gt;
&lt;/reg&gt;
&lt;reg&gt;
&lt;type&gt;rev&lt;/type&gt;
&lt;impl&gt;present&lt;/impl&gt;
&lt;name&gt;w&lt;/name&gt;
&lt;location&gt;slave_port&lt;/location&gt;
&lt;/reg&gt;
&lt;reg&gt;
&lt;type&gt;rev&lt;/type&gt;
&lt;impl&gt;present&lt;/impl&gt;
&lt;name&gt;ar&lt;/name&gt;
&lt;location&gt;slave_port&lt;/location&gt;
&lt;/reg&gt;
&lt;reg&gt;
&lt;type&gt;fwd&lt;/type&gt;
&lt;impl&gt;absent&lt;/impl&gt;
&lt;name&gt;b&lt;/name&gt;
&lt;location&gt;slave_port&lt;/location&gt;
&lt;/reg&gt;
&lt;reg&gt;
&lt;type&gt;fwd&lt;/type&gt;
&lt;impl&gt;absent&lt;/impl&gt;
&lt;name&gt;r&lt;/name&gt;
&lt;location&gt;slave_port&lt;/location&gt;
&lt;/reg&gt;
&lt;reg&gt;
&lt;type&gt;fwd&lt;/type&gt;
&lt;impl&gt;absent&lt;/impl&gt;
&lt;name&gt;aw&lt;/name&gt;
&lt;location&gt;master_port&lt;/location&gt;
&lt;/reg&gt;
&lt;reg&gt;
&lt;type&gt;fwd&lt;/type&gt;
&lt;impl&gt;absent&lt;/impl&gt;
&lt;name&gt;w&lt;/name&gt;
&lt;location&gt;master_port&lt;/location&gt;
&lt;/reg&gt;
&lt;reg&gt;
&lt;type&gt;fwd&lt;/type&gt;
&lt;impl&gt;absent&lt;/impl&gt;
&lt;name&gt;ar&lt;/name&gt;
&lt;location&gt;master_port&lt;/location&gt;
&lt;/reg&gt;
&lt;reg&gt;
&lt;type&gt;fwd&lt;/type&gt;
&lt;impl&gt;absent&lt;/impl&gt;
&lt;name&gt;b&lt;/name&gt;
&lt;location&gt;master_port&lt;/location&gt;
&lt;/reg&gt;
&lt;reg&gt;
&lt;type&gt;fwd&lt;/type&gt;
&lt;impl&gt;absent&lt;/impl&gt;
&lt;name&gt;r&lt;/name&gt;
&lt;location&gt;master_port&lt;/location&gt;
&lt;/reg&gt;
&lt;/amib&gt;
&lt;connect&gt;
&lt;ruser&gt;false&lt;/ruser&gt;
&lt;wuser&gt;false&lt;/wuser&gt;
&lt;src&gt;M1_m&lt;/src&gt;
&lt;awuser&gt;false&lt;/awuser&gt;
&lt;out_trans&gt;16&lt;/out_trans&gt;
&lt;dest&gt;external&lt;/dest&gt;
&lt;src_port&gt;M1_m_m&lt;/src_port&gt;
&lt;protocol&gt;axi&lt;/protocol&gt;
&lt;buser&gt;false&lt;/buser&gt;
&lt;out_reads&gt;16&lt;/out_reads&gt;
&lt;lock&gt;false&lt;/lock&gt;
&lt;out_writes&gt;16&lt;/out_writes&gt;
&lt;dest_port&gt;M1_m_m&lt;/dest_port&gt;
&lt;aruser&gt;false&lt;/aruser&gt;
&lt;/connect&gt;
&lt;connect&gt;
&lt;ruser&gt;false&lt;/ruser&gt;
&lt;wuser&gt;false&lt;/wuser&gt;
&lt;src&gt;external&lt;/src&gt;
&lt;awuser&gt;false&lt;/awuser&gt;
&lt;out_trans&gt;32&lt;/out_trans&gt;
&lt;dest&gt;M1_m&lt;/dest&gt;
&lt;src_port&gt;M1_m_s&lt;/src_port&gt;
&lt;protocol&gt;axi&lt;/protocol&gt;
&lt;buser&gt;false&lt;/buser&gt;
&lt;out_reads&gt;16&lt;/out_reads&gt;
&lt;lock&gt;false&lt;/lock&gt;
&lt;out_writes&gt;16&lt;/out_writes&gt;
&lt;dest_port&gt;M1_m_s&lt;/dest_port&gt;
&lt;aruser&gt;false&lt;/aruser&gt;
&lt;/connect&gt;
&lt;/periph&gt;
</NICConfigFile>
</Architecture>
<Deliverables>
<IPXACT/>
<RTL/>
<TestBench/>
<Reports/>
</Deliverables>
</ConfiguredComponent>
\ No newline at end of file
verif/cocotb/sram_chiplet_cocotb.v 0 → 100644
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