diff --git a/.gitignore b/.gitignore
index 803f6b9de56f2ce0dd4ffc6209773f99198bd365..36e5e46bb9c92549ae2469ac31d453fc37c74dea 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1,2 +1,19 @@
-./logical/nic400_sram_chiplet
-./logical/nic400_tlx_sram_chiplet
\ No newline at end of file
+.project
+.ecmproject
+
+logical/nic400_sram_chiplet/
+logical/nic400_tlx_sram_chiplet/
+logical/SMC
+logical/shared
+
+simulate
+
+verif/cocotb/sim_build
+verif/cocotb/__pycache__
+verif/cocotb/*.vstf
+verif/cocotb/*.wlf
+verif/cocotb/transcript
+verif/cocotb/results.xml
+verif/cocotb/*.ini
+
+imp
diff --git a/logical/SRAM/verilog/SRAM_wrapper.v b/logical/SRAM/verilog/SRAM_wrapper.v
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/logical/top_sram_chiplet/verilog/top_sram_chiplet.v b/logical/top_sram_chiplet/verilog/top_sram_chiplet.v
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/make.cfg b/make.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..775771ea6530ff887ba1cbe99ecee6902ace25a2
--- /dev/null
+++ b/make.cfg
@@ -0,0 +1 @@
+SIE300_IP_LOGICAL_DIR:=
\ No newline at end of file
diff --git a/socrates/BP301_SRAM/config/SRAM_ctrl.yaml b/socrates/BP301_SRAM/config/SRAM_ctrl.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..ec3ef9fb85d9f7000461193298c47c97cd4537ad
--- /dev/null
+++ b/socrates/BP301_SRAM/config/SRAM_ctrl.yaml
@@ -0,0 +1,140 @@
+#----------------------------------------------------------------------------
+# The confidential and proprietary information contained in this file may
+# only be used by a person authorised under and to the extent permitted
+# by a subsisting licensing agreement from Arm Limited or its affiliates.
+#
+# (C) COPYRIGHT 2019 Arm Limited or its affiliates.
+# ALL RIGHTS RESERVED
+#
+# This entire notice must be reproduced on all copies of this file
+# and copies of this file may only be made by a person if such person is
+# permitted to do so under the terms of a subsisting license agreement
+# from Arm Limited or its affiliates.
+#----------------------------------------------------------------------------
+#
+# Version Information
+#
+# Checked In : Mon Jul 15 17:15:15 2019 +0100
+#
+# Revision : 828f11fd
+#
+# Release Information : CoreLink SIE-300 Generic Global Bundle r1p2-00rel0
+#
+#----------------------------------------------------------------------------
+# Abstract : Configuration file for SIE-300 AXI5 SRAM Controller
+#----------------------------------------------------------------------------
+
+# -----------------------------
+# User Configuration
+# -----------------------------
+
+
+#
+# COMPONENT: Name of the component to configure.
+# Valid values:
+# [sie300_axi5_sram_ctrl]
+#
+COMPONENT: sie300_axi5_sram_ctrl
+
+
+#
+# CONFIG_NAME: Name of the configuration.
+# Each unifiqued element and top is suffixed with
+# _${CONFIG_NAME}
+#
+CONFIG_NAME: sram_chiplet
+
+
+#
+# ADDR_WIDTH: AXI5 Address Bus width
+# Valid values:
+# 14-24
+ADDR_WIDTH: 21
+
+
+#
+# DATA_WIDTH: AXI5 Data Bus width
+# Valid values:
+# [32,64,128,256]
+DATA_WIDTH: 32
+
+
+#
+# ID_WIDTH: AXI5 ID width for all channels
+# Valid values:
+# 2-32
+ID_WIDTH: 4
+
+
+#
+# QCLK_SYNC_EN: Add 2 DFF synchronizer on inputs of clock Q-channel
+# Valid values:
+# - 0 : no synchronizer
+# - 1 : added synchronizer
+QCLK_SYNC_EN: 1
+
+
+#
+# QPWR_SYNC_EN: Add 2 DFF synchronizer on inputs of power Q-channel
+# Valid values:
+# - 0 : no synchronizer
+# - 1 : added synchronizer
+QPWR_SYNC_EN: 1
+
+
+#
+# QEXT_SYNC_EN: Add 2 DFF synchronizer on inputs of external gating Q-channel
+# Valid values:
+# - 0 : no synchronizer
+# - 1 : added synchronizer
+QEXT_SYNC_EN: 1
+
+
+#
+# EXCLUSIVE_MONITORS: Number of Exclusive Access Monitors to observe
+# and track AXI locked transactions
+# Valid values:
+# 0-16 (0 means no locked transaction support)
+EXCLUSIVE_MONITORS: 2
+
+
+#
+# AR_BUF_SIZE: Size of FIFO on AR channel
+# Valid values:
+# 1-16
+AR_BUF_SIZE: 4
+
+
+#
+# AW_BUF_SIZE: Size of FIFO on AW channel
+# Valid values:
+# 1-16
+AW_BUF_SIZE: 4
+
+
+#
+# W_BUF_SIZE: Size of FIFO on W channel
+# Valid values:
+# 1-16
+W_BUF_SIZE: 8
+
+
+#
+# REGISTER_AXI_AR: Enables / disables register stage at the AR FIFO
+# Valid values:
+# [BYPASS,FULL]
+REGISTER_AXI_AR: BYPASS
+
+
+#
+# REGISTER_AXI_R: Enables / disables register stage at the R FIFO
+# Valid values:
+# [BYPASS,FULL]
+REGISTER_AXI_R: BYPASS
+
+
+#
+# AXI5_POISON_EN: Enables / disables AXI5 Data Poisoning support
+# Valid values:
+# [0,1]
+AXI5_POISON_EN: 0
diff --git a/socrates/nic400_sram_chiplet/nic400_sram_chiplet.xml b/socrates/nic400_sram_chiplet/nic400_sram_chiplet.xml
new file mode 100644
index 0000000000000000000000000000000000000000..fe98640e57ed7b538eec921298d96e9935c05945
--- /dev/null
+++ b/socrates/nic400_sram_chiplet/nic400_sram_chiplet.xml
@@ -0,0 +1,1115 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<ConfiguredComponent>
+ <Name>nic400_sram_chiplet</Name>
+ <Suffix>sram_chiplet</Suffix>
+ <ConfigurableComponentRef>
+ <Vendor>arm.com</Vendor>
+ <Library>CoreLink</Library>
+ <Name>nic400</Name>
+ <Version>r1p2</Version>
+ </ConfigurableComponentRef>
+ <Specification>
+ <Parameters>
+ <AWUSERWidth>0</AWUSERWidth>
+ <ARUSERWidth>0</ARUSERWidth>
+ <WUSERWidth>0</WUSERWidth>
+ <BUSERWidth>0</BUSERWidth>
+ <RUSERWidth>0</RUSERWidth>
+ <GlobalIDWidth>1</GlobalIDWidth>
+ <HierarchicalClockGating>false</HierarchicalClockGating>
+ <ClockControllerImplementation>asynchronous</ClockControllerImplementation>
+ <RSBCentralRing>false</RSBCentralRing>
+ <DefaultProtocol>axi4</DefaultProtocol>
+ <UppercaseRTLSignals>true</UppercaseRTLSignals>
+ <Taxonomy>master_slave</Taxonomy>
+ <QoSEnabled>false</QoSEnabled>
+ <QVNEnabled>false</QVNEnabled>
+ </Parameters>
+ <Domains>
+ <VoltageDomains>
+ <VoltageDomain>
+ <Name>vd0</Name>
+ </VoltageDomain>
+ </VoltageDomains>
+ <PowerDomains>
+ <PowerDomain>
+ <Name>pd0</Name>
+ <PowerDomainType>AlwaysOn</PowerDomainType>
+ <VoltageDomainRef>vd0</VoltageDomainRef>
+ </PowerDomain>
+ </PowerDomains>
+ <ClockDomains>
+ <ClockDomain>
+ <Name>clk0</Name>
+ <ClockDomainType>physical</ClockDomainType>
+ <PowerDomainRef>pd0</PowerDomainRef>
+ </ClockDomain>
+ </ClockDomains>
+ <ClockRelations/>
+ </Domains>
+ <Groups>
+ <ExternalGroups/>
+ <APBGroups>
+ <APBGroup>
+ <Name>apb_group0</Name>
+ <ClockRef>clk0</ClockRef>
+ <ReadIssuingAPB>1</ReadIssuingAPB>
+ <WriteIssuingAPB>1</WriteIssuingAPB>
+ <TotalIssuingAPB>1</TotalIssuingAPB>
+ <LockSupport>false</LockSupport>
+ </APBGroup>
+ </APBGroups>
+ </Groups>
+ <Interfaces>
+ <SlaveInterface>
+ <Name>AXI_CHIPLET_IN</Name>
+ <AXI4SlaveProtocol>
+ <AddressWidth>32</AddressWidth>
+ <DataWidth>32</DataWidth>
+ <VIDWidth>0</VIDWidth>
+ <MultiRegion>false</MultiRegion>
+ <TrustZoneSlave>non_secure</TrustZoneSlave>
+ <ReadAcceptance>16</ReadAcceptance>
+ <WriteAcceptance>16</WriteAcceptance>
+ <QoSTypeAXI>fixed</QoSTypeAXI>
+ <QoSValue>0</QoSValue>
+ <TransactionRateRegulation>false</TransactionRateRegulation>
+ <OutstandingTransactionRegulation>false</OutstandingTransactionRegulation>
+ <LatencyPeriodRegulation>false</LatencyPeriodRegulation>
+ <VNExternal>false</VNExternal>
+ </AXI4SlaveProtocol>
+ <GeographicDomainRef>gd0</GeographicDomainRef>
+ <ClockRef>clk0</ClockRef>
+ <MultiPorted>false</MultiPorted>
+ <CyclicDependencyAvoidanceScheme>single_slave</CyclicDependencyAvoidanceScheme>
+ <LowLatency>false</LowLatency>
+ </SlaveInterface>
+ <MasterInterface>
+ <Name>AXI_SRAM</Name>
+ <AXI4MasterProtocol>
+ <AddressWidth>32</AddressWidth>
+ <DataWidth>32</DataWidth>
+ <IDWidth>0</IDWidth>
+ <MultiRegion>false</MultiRegion>
+ <TrustZoneMaster>non_secure</TrustZoneMaster>
+ <ReadIssuing>1</ReadIssuing>
+ <WriteIssuing>1</WriteIssuing>
+ <TotalIssuing>1</TotalIssuing>
+ <MultiPorted>false</MultiPorted>
+ <IDWidthReduction>true</IDWidthReduction>
+ <OutputSignals>false</OutputSignals>
+ <VNExternal>false</VNExternal>
+ </AXI4MasterProtocol>
+ <GeographicDomainRef>gd0</GeographicDomainRef>
+ <ClockRef>clk0</ClockRef>
+ </MasterInterface>
+ <MasterInterface>
+ <Name>APB_PVT</Name>
+ <APB4MasterProtocol>
+ <AddressWidth>32</AddressWidth>
+ <DataWidth>32</DataWidth>
+ <TrustZoneMasterAPB>non_secure</TrustZoneMasterAPB>
+ <APBGroupRef>apb_group0</APBGroupRef>
+ </APB4MasterProtocol>
+ <GeographicDomainRef>gd0</GeographicDomainRef>
+ <ClockRef>clk0</ClockRef>
+ </MasterInterface>
+ <SlaveInterface>
+ <Name>AHB_ADP</Name>
+ <AHBLiteTargetSlaveProtocol>
+ <AddressWidth>32</AddressWidth>
+ <DataWidth>32</DataWidth>
+ <RUSEREnabled>false</RUSEREnabled>
+ <WUSEREnabled>false</WUSEREnabled>
+ <LockSupport>false</LockSupport>
+ <TrustZoneSlaveAHB>non_secure</TrustZoneSlaveAHB>
+ <ReadAcceptanceAHB>1</ReadAcceptanceAHB>
+ <WriteAcceptance>4</WriteAcceptance>
+ <QoSTypeAHB>fixed</QoSTypeAHB>
+ <QoSValue>0</QoSValue>
+ <TransactionRateRegulation>false</TransactionRateRegulation>
+ <OutstandingTransactionRegulation>false</OutstandingTransactionRegulation>
+ <LatencyPeriodRegulation>false</LatencyPeriodRegulation>
+ <EnableEarlyWriteResponse>true</EnableEarlyWriteResponse>
+ <BrokenBursts>false</BrokenBursts>
+ </AHBLiteTargetSlaveProtocol>
+ <GeographicDomainRef>gd0</GeographicDomainRef>
+ <ClockRef>clk0</ClockRef>
+ <MultiPorted>false</MultiPorted>
+ <CyclicDependencyAvoidanceScheme>single_slave</CyclicDependencyAvoidanceScheme>
+ <LowLatency>false</LowLatency>
+ </SlaveInterface>
+ </Interfaces>
+ <MemoryMaps>
+ <MemoryMap>
+ <Name>mm0</Name>
+ <MemoryMapSource>
+ <InterfaceRef>AXI_CHIPLET_IN</InterfaceRef>
+ </MemoryMapSource>
+ <MemoryMapSource>
+ <InterfaceRef>AHB_ADP</InterfaceRef>
+ </MemoryMapSource>
+ <MappedBlock>
+ <InterfaceRef>AXI_SRAM</InterfaceRef>
+ <Offset>0</Offset>
+ <Range>65536</Range>
+ <Visibility>true</Visibility>
+ </MappedBlock>
+ <MappedBlock>
+ <InterfaceRef>APB_PVT</InterfaceRef>
+ <Offset>65536</Offset>
+ <Range>4096</Range>
+ <Visibility>true</Visibility>
+ </MappedBlock>
+ </MemoryMap>
+ </MemoryMaps>
+ <Paths>
+ <Path>
+ <Source>
+ <InterfaceRef>AXI_CHIPLET_IN</InterfaceRef>
+ </Source>
+ <Targets>
+ <Target>
+ <InterfaceRef>AXI_SRAM</InterfaceRef>
+ </Target>
+ <Target>
+ <InterfaceRef>APB_PVT</InterfaceRef>
+ </Target>
+ </Targets>
+ </Path>
+ <Path>
+ <Source>
+ <InterfaceRef>AHB_ADP</InterfaceRef>
+ </Source>
+ <Targets>
+ <Target>
+ <InterfaceRef>APB_PVT</InterfaceRef>
+ </Target>
+ <Target>
+ <InterfaceRef>AXI_SRAM</InterfaceRef>
+ </Target>
+ </Targets>
+ </Path>
+ </Paths>
+ <VirtualNetworks/>
+ </Specification>
+ <Architecture>
+ <NICConfigFile><periph>
+ <product_version_info major_group="bu" major_revision="1" major_version="00" minor_code="50000" minor_revision="2" minor_version="0" part_quality="rel" product_code="nic400" />
+ <validator_version_info major_revision="22" minor_revision="1" />
+ <global>
+ <address0x0 def="true">bottom</address0x0>
+ <aruser_width>0</aruser_width>
+ <awuser_width>0</awuser_width>
+ <buser_width>0</buser_width>
+ <cc_type>async</cc_type>
+ <default_protocol>axi4</default_protocol>
+ <dpe_glb_enable def="true">false</dpe_glb_enable>
+ <dpe_status>false</dpe_status>
+ <dpe_width def="true">5</dpe_width>
+ <gen_caps>true</gen_caps>
+ <hcg_en>false</hcg_en>
+ <license_status>unlicensed_nic</license_status>
+ <periph_id3 def="true">0</periph_id3>
+ <pl_id_width>1</pl_id_width>
+ <qos_status>false</qos_status>
+ <rsb_arch_central_ring>false</rsb_arch_central_ring>
+ <ruser_width>0</ruser_width>
+ <sas_visible def="true">false</sas_visible>
+ <start_iid>0</start_iid>
+ <taxonomy>masterslave</taxonomy>
+ <thin_links_status def="true">false</thin_links_status>
+ <uppercase_ext_sig>true</uppercase_ext_sig>
+ <virtual_networks />
+ <virtual_networks_status>false</virtual_networks_status>
+ <wuser_width>0</wuser_width>
+ </global>
+ <clocks>
+ <domain freq="100">clk0</domain>
+ </clocks>
+ <asib>
+ <address_ranges>
+ <name>mm0</name>
+ <range>
+ <addr_max>0xFFFF</addr_max>
+ <addr_min>0x0</addr_min>
+ <remap>
+ <bit>default</bit>
+ <present>true</present>
+ <region>0</region>
+ <target>AXI_SRAM</target>
+ </remap>
+ </range>
+ <range>
+ <addr_max>0x10FFF</addr_max>
+ <addr_min>0x10000</addr_min>
+ <remap>
+ <bit>default</bit>
+ <present>true</present>
+ <region>0</region>
+ <target>APB_PVT</target>
+ </remap>
+ </range>
+ </address_ranges>
+ <apb_config>false</apb_config>
+ <apb_slave_no def="true">2</apb_slave_no>
+ <cds>singleslave</cds>
+ <clock_boundary>none</clock_boundary>
+ <clock_domain_name_master_if>clk0</clock_domain_name_master_if>
+ <clock_domain_name_slave_if>clk0</clock_domain_name_slave_if>
+ <master_if_data_width>32</master_if_data_width>
+ <multi_ported>false</multi_ported>
+ <multi_region>false</multi_region>
+ <name>AXI_CHIPLET_IN</name>
+ <protocol>axi4</protocol>
+ <qos_config>
+ <hard>disable</hard>
+ <lqv>disable</lqv>
+ <pot>disable</pot>
+ </qos_config>
+ <qv>
+ <type>fixed</type>
+ <value>0</value>
+ </qv>
+ <reg>
+ <impl>present</impl>
+ <location>slave_port</location>
+ <name>aw</name>
+ <type>rev</type>
+ </reg>
+ <reg>
+ <impl>present</impl>
+ <location>slave_port</location>
+ <name>w</name>
+ <type>rev</type>
+ </reg>
+ <reg>
+ <impl>present</impl>
+ <location>slave_port</location>
+ <name>ar</name>
+ <type>rev</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>aw</name>
+ <type>fifo</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>ar</name>
+ <type>fifo</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>r</name>
+ <type>fifo</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>w</name>
+ <type>fifo</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>b</name>
+ <type>fifo</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>master_port</location>
+ <name>aw</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>master_port</location>
+ <name>ar</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>master_port</location>
+ <name>r</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>master_port</location>
+ <name>w</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>master_port</location>
+ <name>b</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>slave_port</location>
+ <name>r</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>slave_port</location>
+ <name>b</name>
+ <type def="true">full</type>
+ </reg>
+ <slave_if_addr_width>32</slave_if_addr_width>
+ <slave_if_data_width>32</slave_if_data_width>
+ <token_prerequest def="true">false</token_prerequest>
+ <token_prerequest_bridge def="true">false</token_prerequest_bridge>
+ <trustzone>nsec</trustzone>
+ <vid_width>0</vid_width>
+ <vn_external>none</vn_external>
+ <vn_external_bridge>none</vn_external_bridge>
+ <x>0</x>
+ <y>20</y>
+ <master_if_port_name>AXI_CHIPLET_IN_m</master_if_port_name>
+ <slave_if_port_name>AXI_CHIPLET_IN_s</slave_if_port_name>
+ </asib>
+ <asib>
+ <address_ranges>
+ <name>mm0</name>
+ <range>
+ <addr_max>0xFFFF</addr_max>
+ <addr_min>0x0</addr_min>
+ <remap>
+ <bit>default</bit>
+ <present>true</present>
+ <region>0</region>
+ <target>AXI_SRAM</target>
+ </remap>
+ </range>
+ <range>
+ <addr_max>0x10FFF</addr_max>
+ <addr_min>0x10000</addr_min>
+ <remap>
+ <bit>default</bit>
+ <present>true</present>
+ <region>0</region>
+ <target>APB_PVT</target>
+ </remap>
+ </range>
+ </address_ranges>
+ <apb_config>false</apb_config>
+ <apb_slave_no def="true">2</apb_slave_no>
+ <broken_bursts>false</broken_bursts>
+ <cds>singleslave</cds>
+ <clock_boundary>none</clock_boundary>
+ <clock_domain_name_master_if>clk0</clock_domain_name_master_if>
+ <clock_domain_name_slave_if>clk0</clock_domain_name_slave_if>
+ <ewr_incr_promotion>true</ewr_incr_promotion>
+ <master_if_data_width>32</master_if_data_width>
+ <multi_ported>false</multi_ported>
+ <multi_region>false</multi_region>
+ <name>AHB_ADP</name>
+ <protocol>ahb_s</protocol>
+ <qos_config>
+ <hard>disable</hard>
+ <lqv>disable</lqv>
+ <pot>disable</pot>
+ </qos_config>
+ <qv>
+ <type>fixed</type>
+ <value>0</value>
+ </qv>
+ <reg>
+ <impl>present</impl>
+ <location>slave_port</location>
+ <name>w</name>
+ <type>rev</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>master_port</location>
+ <name>aw</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>master_port</location>
+ <name>ar</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>master_port</location>
+ <name>r</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>master_port</location>
+ <name>w</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>master_port</location>
+ <name>b</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>slave_port</location>
+ <name>a</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>slave_port</location>
+ <name>d</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>a</name>
+ <type>fifo</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>d</name>
+ <type>fifo</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>w</name>
+ <type>fifo</type>
+ </reg>
+ <slave_if_addr_width>32</slave_if_addr_width>
+ <slave_if_data_width>32</slave_if_data_width>
+ <token_prerequest def="true">false</token_prerequest>
+ <token_prerequest_bridge def="true">false</token_prerequest_bridge>
+ <trustzone>nsec</trustzone>
+ <vid_width>0</vid_width>
+ <vn_external>none</vn_external>
+ <vn_external_bridge>none</vn_external_bridge>
+ <x>0</x>
+ <y>40</y>
+ <master_if_port_name>AHB_ADP_m</master_if_port_name>
+ <slave_if_port_name>AHB_ADP_s</slave_if_port_name>
+ </asib>
+ <amib>
+ <apb_config>false</apb_config>
+ <apb_slave_no>65</apb_slave_no>
+ <clock_boundary>none</clock_boundary>
+ <clock_domain_name_master_if>clk0</clock_domain_name_master_if>
+ <clock_domain_name_slave_if>clk0</clock_domain_name_slave_if>
+ <compress_id>true</compress_id>
+ <dest_type>peripheral</dest_type>
+ <master_if_addr_width>32</master_if_addr_width>
+ <master_if_data_width>32</master_if_data_width>
+ <multi_ported>false</multi_ported>
+ <multi_region>false</multi_region>
+ <name>AXI_SRAM</name>
+ <protocol>axi4</protocol>
+ <qv_out>false</qv_out>
+ <reg>
+ <impl>present</impl>
+ <location>master_port</location>
+ <name>w</name>
+ <type>rev</type>
+ </reg>
+ <reg>
+ <impl>present</impl>
+ <location>master_port</location>
+ <name>b</name>
+ <type>rev</type>
+ </reg>
+ <reg>
+ <impl>present</impl>
+ <location>master_port</location>
+ <name>r</name>
+ <type>rev</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>slave_port</location>
+ <name>aw</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>aw</name>
+ <type>fifo</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>master_port</location>
+ <name>aw</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>slave_port</location>
+ <name>ar</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>ar</name>
+ <type>fifo</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>master_port</location>
+ <name>ar</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>slave_port</location>
+ <name>r</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>r</name>
+ <type>fifo</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>slave_port</location>
+ <name>w</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>w</name>
+ <type>fifo</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>slave_port</location>
+ <name>b</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>b</name>
+ <type>fifo</type>
+ </reg>
+ <slave_if_data_width>32</slave_if_data_width>
+ <token_prerequest def="true">false</token_prerequest>
+ <token_prerequest_bridge def="true">false</token_prerequest_bridge>
+ <trustzone>nsec</trustzone>
+ <vn_external>none</vn_external>
+ <vn_external_bridge>none</vn_external_bridge>
+ <x>0</x>
+ <y>20</y>
+ <master_if_port_name>AXI_SRAM_m</master_if_port_name>
+ <slave_if_port_name>AXI_SRAM_s</slave_if_port_name>
+ </amib>
+ <amib>
+ <apb_config>false</apb_config>
+ <apb_port>
+ <clock_domain>clk0</clock_domain>
+ <name>APB_PVT</name>
+ <trustzone>nsec</trustzone>
+ <x>0</x>
+ <y>0</y>
+ </apb_port>
+ <apb_slave_no>64</apb_slave_no>
+ <clock_boundary>none</clock_boundary>
+ <clock_domain_name_master_if>clk0</clock_domain_name_master_if>
+ <clock_domain_name_slave_if>clk0</clock_domain_name_slave_if>
+ <compress_id def="true">false</compress_id>
+ <dest_type>peripheral</dest_type>
+ <master_if_addr_width>32</master_if_addr_width>
+ <master_if_data_width>32</master_if_data_width>
+ <multi_ported>false</multi_ported>
+ <multi_region>false</multi_region>
+ <name>apb_group0</name>
+ <protocol>apb</protocol>
+ <qv_out>false</qv_out>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>slave_port</location>
+ <name>aw</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>slave_port</location>
+ <name>ar</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>slave_port</location>
+ <name>r</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>slave_port</location>
+ <name>w</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>slave_port</location>
+ <name>b</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>master_port</location>
+ <name>a</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>master_port</location>
+ <name>d</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <location>master_port</location>
+ <name>w</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>a</name>
+ <type>fifo</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>d</name>
+ <type>fifo</type>
+ </reg>
+ <reg>
+ <depth def="true">2</depth>
+ <impl def="true">absent</impl>
+ <location>boundary</location>
+ <name>w</name>
+ <type>fifo</type>
+ </reg>
+ <slave_if_data_width>32</slave_if_data_width>
+ <token_prerequest def="true">false</token_prerequest>
+ <token_prerequest_bridge def="true">false</token_prerequest_bridge>
+ <trustzone>nsec</trustzone>
+ <vn_external def="true">none</vn_external>
+ <vn_external_bridge def="true">none</vn_external_bridge>
+ <x>0</x>
+ <y>40</y>
+ <master_if_port_name>APB_PVT</master_if_port_name>
+ <slave_if_port_name>apb_group0_s</slave_if_port_name>
+ </amib>
+ <inter>
+ <clock_domain>clk0</clock_domain>
+ <data_width>32</data_width>
+ <expanded>false</expanded>
+ <height>40</height>
+ <impl>mlayer</impl>
+ <master_if>
+ <name>axi_m_0</name>
+ <post_arb_reg>absent</post_arb_reg>
+ <x>0</x>
+ <y>63</y>
+ </master_if>
+ <master_if>
+ <name>axi_m_1</name>
+ <post_arb_reg>absent</post_arb_reg>
+ <x>0</x>
+ <y>83</y>
+ </master_if>
+ <master_if>
+ <name>axi_m_2</name>
+ <post_arb_reg>absent</post_arb_reg>
+ <x>0</x>
+ <y>103</y>
+ </master_if>
+ <name>bm0</name>
+ <protocol>axi4</protocol>
+ <slave_if>
+ <name>axi_s_0</name>
+ <x>0</x>
+ <y>63</y>
+ </slave_if>
+ <slave_if>
+ <name>axi_s_1</name>
+ <x>0</x>
+ <y>83</y>
+ </slave_if>
+ <sparse>
+ <cds>singleslave</cds>
+ <sas def="true">false</sas>
+ <slave_if_port>axi_s_0</slave_if_port>
+ <master_if_port>
+ <name>axi_m_0</name>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>aw</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>ar</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>r</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>w</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>b</name>
+ <type def="true">full</type>
+ </reg>
+ </master_if_port>
+ <master_if_port>
+ <name>axi_m_1</name>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>aw</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>ar</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>r</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>w</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>b</name>
+ <type def="true">full</type>
+ </reg>
+ </master_if_port>
+ <master_if_port>
+ <name>axi_m_2</name>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>aw</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>ar</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>r</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>w</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>b</name>
+ <type def="true">full</type>
+ </reg>
+ </master_if_port>
+ </sparse>
+ <sparse>
+ <cds>singleslave</cds>
+ <sas def="true">false</sas>
+ <slave_if_port>axi_s_1</slave_if_port>
+ <master_if_port>
+ <name>axi_m_0</name>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>aw</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>ar</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>r</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>w</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>b</name>
+ <type def="true">full</type>
+ </reg>
+ </master_if_port>
+ <master_if_port>
+ <name>axi_m_1</name>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>aw</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>ar</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>r</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>w</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>b</name>
+ <type def="true">full</type>
+ </reg>
+ </master_if_port>
+ <master_if_port>
+ <name>axi_m_2</name>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>aw</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>ar</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>r</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>w</name>
+ <type def="true">full</type>
+ </reg>
+ <reg>
+ <impl def="true">absent</impl>
+ <name>b</name>
+ <type def="true">full</type>
+ </reg>
+ </master_if_port>
+ </sparse>
+ <type>busmatrix</type>
+ <width>0</width>
+ <x>500</x>
+ <y>45</y>
+ <master_if_port_name>axi_m_0,axi_m_1,axi_m_2</master_if_port_name>
+ <slave_if_port_name>axi_s_0,axi_s_1</slave_if_port_name>
+ </inter>
+ <inter>
+ <name>ds_1</name>
+ <slave_if>
+ <name>axi_s_0</name>
+ <x>0</x>
+ <y>0</y>
+ </slave_if>
+ <type>default_slave</type>
+ <x>500</x>
+ <y>500</y>
+ <master_if_port_name />
+ <slave_if_port_name>axi_s_0</slave_if_port_name>
+ </inter>
+ <connect>
+ <aruser>false</aruser>
+ <awuser>false</awuser>
+ <buser>false</buser>
+ <dest>AXI_CHIPLET_IN</dest>
+ <dest_port>AXI_CHIPLET_IN_s</dest_port>
+ <lock>false</lock>
+ <out_reads>16</out_reads>
+ <out_trans>32</out_trans>
+ <out_writes>16</out_writes>
+ <protocol>axi4</protocol>
+ <ruser>false</ruser>
+ <src>external</src>
+ <src_port>AXI_CHIPLET_IN</src_port>
+ <wuser>false</wuser>
+ </connect>
+ <connect>
+ <aruser>false</aruser>
+ <awuser>false</awuser>
+ <buser>false</buser>
+ <dest>AHB_ADP</dest>
+ <dest_port>AHB_ADP_s</dest_port>
+ <lock>false</lock>
+ <out_reads>1</out_reads>
+ <out_trans>5</out_trans>
+ <out_writes>4</out_writes>
+ <protocol>ahb_s</protocol>
+ <ruser>false</ruser>
+ <src>external</src>
+ <src_port>AHB_ADP</src_port>
+ <wuser>false</wuser>
+ </connect>
+ <connect>
+ <aruser>false</aruser>
+ <awuser>false</awuser>
+ <buser>false</buser>
+ <dest>external</dest>
+ <dest_port>AXI_SRAM</dest_port>
+ <lock>false</lock>
+ <out_reads>1</out_reads>
+ <out_trans>1</out_trans>
+ <out_writes>1</out_writes>
+ <protocol>axi4</protocol>
+ <ruser>false</ruser>
+ <src>AXI_SRAM</src>
+ <src_port>AXI_SRAM_m</src_port>
+ <wuser>false</wuser>
+ </connect>
+ <connect>
+ <aruser>false</aruser>
+ <awuser>false</awuser>
+ <buser>false</buser>
+ <dest>external</dest>
+ <dest_port>APB_PVT</dest_port>
+ <lock>false</lock>
+ <out_reads>1</out_reads>
+ <out_trans>1</out_trans>
+ <out_writes>1</out_writes>
+ <protocol>apb4</protocol>
+ <ruser>false</ruser>
+ <src>apb_group0</src>
+ <src_port>APB_PVT</src_port>
+ <wuser>false</wuser>
+ </connect>
+ <connect>
+ <dest>bm0</dest>
+ <dest_port>axi_s_0</dest_port>
+ <lock>false</lock>
+ <out_reads def="true">16</out_reads>
+ <out_trans>32</out_trans>
+ <out_writes def="true">16</out_writes>
+ <protocol>axi4</protocol>
+ <src>AXI_CHIPLET_IN</src>
+ <src_port>AXI_CHIPLET_IN_m</src_port>
+ </connect>
+ <connect>
+ <dest>apb_group0</dest>
+ <dest_port>apb_group0_s</dest_port>
+ <lock>false</lock>
+ <out_reads def="true">2</out_reads>
+ <out_trans def="true">2</out_trans>
+ <out_writes def="true">2</out_writes>
+ <protocol>axi4</protocol>
+ <src>bm0</src>
+ <src_port>axi_m_0</src_port>
+ </connect>
+ <connect>
+ <dest>AXI_SRAM</dest>
+ <dest_port>AXI_SRAM_s</dest_port>
+ <lock>false</lock>
+ <out_reads>1</out_reads>
+ <out_trans>1</out_trans>
+ <out_writes>1</out_writes>
+ <protocol>axi4</protocol>
+ <src>bm0</src>
+ <src_port>axi_m_1</src_port>
+ </connect>
+ <connect>
+ <dest>bm0</dest>
+ <dest_port>axi_s_1</dest_port>
+ <lock>false</lock>
+ <out_reads def="true">1</out_reads>
+ <out_trans>3</out_trans>
+ <out_writes def="true">2</out_writes>
+ <protocol>axi4</protocol>
+ <src>AHB_ADP</src>
+ <src_port>AHB_ADP_m</src_port>
+ </connect>
+ <connect>
+ <dest>ds_1</dest>
+ <dest_port>axi_s_0</dest_port>
+ <lock>false</lock>
+ <out_reads>1</out_reads>
+ <out_trans>2</out_trans>
+ <out_writes>1</out_writes>
+ <protocol>axi4</protocol>
+ <src>bm0</src>
+ <src_port>axi_m_2</src_port>
+ </connect>
+ <architecture>
+ <link>
+ <slave_if>
+ <name>AXI_CHIPLET_IN</name>
+ <master_if>AXI_SRAM</master_if>
+ <master_if>apb_group0</master_if>
+ <master_if>APB_PVT<parent>apb_group0</parent>
+ </master_if>
+ </slave_if>
+ </link>
+ <link>
+ <slave_if>
+ <name>AHB_ADP</name>
+ <master_if>AXI_SRAM</master_if>
+ <master_if>apb_group0</master_if>
+ <master_if>APB_PVT<parent>apb_group0</parent>
+ </master_if>
+ </slave_if>
+ </link>
+ </architecture>
+</periph>
+</NICConfigFile>
+ </Architecture>
+ <Deliverables>
+ <IPXACT/>
+ <RTL/>
+ <TestBench/>
+ <Reports/>
+ </Deliverables>
+</ConfiguredComponent>
\ No newline at end of file
diff --git a/socrates/nic400_tb/nic400_tb.xml b/socrates/nic400_tb/nic400_tb.xml
new file mode 100644
index 0000000000000000000000000000000000000000..e5ed83f8b9f70e1d785c26052daca3c1018b88be
--- /dev/null
+++ b/socrates/nic400_tb/nic400_tb.xml
@@ -0,0 +1,67 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<ConfiguredComponent>
+ <Name>nic400_tb</Name>
+ <Suffix>tb</Suffix>
+ <ConfigurableComponentRef>
+ <Vendor>arm.com</Vendor>
+ <Library>CoreLink</Library>
+ <Name>nic400</Name>
+ <Version>r1p2</Version>
+ </ConfigurableComponentRef>
+ <Specification>
+ <Parameters>
+ <AWUSERWidth>0</AWUSERWidth>
+ <ARUSERWidth>0</ARUSERWidth>
+ <WUSERWidth>0</WUSERWidth>
+ <BUSERWidth>0</BUSERWidth>
+ <RUSERWidth>0</RUSERWidth>
+ <GlobalIDWidth>0</GlobalIDWidth>
+ <HierarchicalClockGating>false</HierarchicalClockGating>
+ <ClockControllerImplementation>asynchronous</ClockControllerImplementation>
+ <RSBCentralRing>false</RSBCentralRing>
+ <DefaultProtocol>axi4</DefaultProtocol>
+ <UppercaseRTLSignals>true</UppercaseRTLSignals>
+ <Taxonomy>master_slave</Taxonomy>
+ <QoSEnabled>false</QoSEnabled>
+ <QVNEnabled>false</QVNEnabled>
+ </Parameters>
+ <Domains>
+ <VoltageDomains>
+ <VoltageDomain>
+ <Name>vd0</Name>
+ </VoltageDomain>
+ </VoltageDomains>
+ <PowerDomains>
+ <PowerDomain>
+ <Name>pd0</Name>
+ <PowerDomainType>AlwaysOn</PowerDomainType>
+ <VoltageDomainRef>vd0</VoltageDomainRef>
+ </PowerDomain>
+ </PowerDomains>
+ <ClockDomains>
+ <ClockDomain>
+ <Name>clk0</Name>
+ <ClockDomainType>physical</ClockDomainType>
+ <PowerDomainRef>pd0</PowerDomainRef>
+ </ClockDomain>
+ </ClockDomains>
+ <ClockRelations/>
+ </Domains>
+ <Groups>
+ <ExternalGroups/>
+ <APBGroups/>
+ </Groups>
+ <Interfaces/>
+ <MemoryMaps>
+ </MemoryMaps>
+ <Paths/>
+ <VirtualNetworks/>
+ </Specification>
+ <Architecture/>
+ <Deliverables>
+ <IPXACT/>
+ <RTL/>
+ <TestBench/>
+ <Reports/>
+ </Deliverables>
+</ConfiguredComponent>
\ No newline at end of file
diff --git a/socrates/nic400_tlx_sram_chiplet/nic400_tlx_sram_chiplet.xml b/socrates/nic400_tlx_sram_chiplet/nic400_tlx_sram_chiplet.xml
new file mode 100644
index 0000000000000000000000000000000000000000..281f5543a27913af8ca9dc3cdee38fe75d505afe
--- /dev/null
+++ b/socrates/nic400_tlx_sram_chiplet/nic400_tlx_sram_chiplet.xml
@@ -0,0 +1,420 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<ConfiguredComponent>
+ <Name>nic400_tlx_sram_chiplet</Name>
+ <Suffix>sram_chiplet</Suffix>
+ <ConfigurableComponentRef>
+ <Vendor>arm.com</Vendor>
+ <Library>CoreLink</Library>
+ <Name>nic400_tlx</Name>
+ <Version>r1p2</Version>
+ </ConfigurableComponentRef>
+ <Specification>
+ <Parameters>
+ <ARUSERWidth>0</ARUSERWidth>
+ <AWUSERWidth>0</AWUSERWidth>
+ <RUSERWidth>0</RUSERWidth>
+ <WUSERWidth>0</WUSERWidth>
+ <BUSERWidth>0</BUSERWidth>
+ <IDWidth>4</IDWidth>
+ <AddressWidth>32</AddressWidth>
+ <SlaveDataWidth>32</SlaveDataWidth>
+ <MasterDataWidth>32</MasterDataWidth>
+ <SlaveReadAcceptance>16</SlaveReadAcceptance>
+ <SlaveWriteAcceptance>16</SlaveWriteAcceptance>
+ <MasterReadIssuing>16</MasterReadIssuing>
+ <MasterWriteIssuing>16</MasterWriteIssuing>
+ <MasterTotalIssuing>16</MasterTotalIssuing>
+ <MultiRegion>false</MultiRegion>
+ <LockSupport>false</LockSupport>
+ <SLAVE_PROTOCOL>AXI</SLAVE_PROTOCOL>
+ <MASTER_PROTOCOL>AXI</MASTER_PROTOCOL>
+ <EarlyWriteResponse>true</EarlyWriteResponse>
+ <AllowBrokenBurst>false</AllowBrokenBurst>
+ <SLAVE_CLOCK>clk_s</SLAVE_CLOCK>
+ <MASTER_CLOCK>clk_m</MASTER_CLOCK>
+ <FW_USER_DEFINED_WIDTH>8</FW_USER_DEFINED_WIDTH>
+ <FW_PACKING_STRATEGY>widest_div_4</FW_PACKING_STRATEGY>
+ <FW_TLX_TIMING_CLOSURE>false</FW_TLX_TIMING_CLOSURE>
+ <REV_PACKING_STRATEGY>widest_div_4</REV_PACKING_STRATEGY>
+ <REV_USER_DEFINED_WIDTH>8</REV_USER_DEFINED_WIDTH>
+ <REV_TLX_TIMING_CLOSURE>false</REV_TLX_TIMING_CLOSURE>
+ <AWSlavePortRegister>present</AWSlavePortRegister>
+ <AWSlavePortRegisterType>rev</AWSlavePortRegisterType>
+ <AWMasterPortRegister>absent</AWMasterPortRegister>
+ <AWMasterPortRegisterType>fwd</AWMasterPortRegisterType>
+ <AWBoundaryBuffering>absent</AWBoundaryBuffering>
+ <AWBoundaryBufferingDepth>2</AWBoundaryBufferingDepth>
+ <AWCreditBuffers>6</AWCreditBuffers>
+ <ARSlavePortRegister>present</ARSlavePortRegister>
+ <ARSlavePortRegisterType>rev</ARSlavePortRegisterType>
+ <ARMasterPortRegister>absent</ARMasterPortRegister>
+ <ARMasterPortRegisterType>fwd</ARMasterPortRegisterType>
+ <ARBoundaryBuffering>absent</ARBoundaryBuffering>
+ <ARBoundaryBufferingDepth>2</ARBoundaryBufferingDepth>
+ <ARCreditBuffers>6</ARCreditBuffers>
+ <WSlavePortRegister>present</WSlavePortRegister>
+ <WSlavePortRegisterType>rev</WSlavePortRegisterType>
+ <WMasterPortRegister>absent</WMasterPortRegister>
+ <WMasterPortRegisterType>fwd</WMasterPortRegisterType>
+ <WBoundaryBuffering>absent</WBoundaryBuffering>
+ <WBoundaryBufferingDepth>2</WBoundaryBufferingDepth>
+ <WCreditBuffers>6</WCreditBuffers>
+ <RSlavePortRegister>absent</RSlavePortRegister>
+ <RSlavePortRegisterType>fwd</RSlavePortRegisterType>
+ <RMasterPortRegister>absent</RMasterPortRegister>
+ <RMasterPortRegisterType>fwd</RMasterPortRegisterType>
+ <RBoundaryBuffering>absent</RBoundaryBuffering>
+ <RBoundaryBufferingDepth>2</RBoundaryBufferingDepth>
+ <RCreditBuffers>6</RCreditBuffers>
+ <BSlavePortRegister>absent</BSlavePortRegister>
+ <BSlavePortRegisterType>fwd</BSlavePortRegisterType>
+ <BMasterPortRegister>absent</BMasterPortRegister>
+ <BMasterPortRegisterType>fwd</BMasterPortRegisterType>
+ <BBoundaryBuffering>absent</BBoundaryBuffering>
+ <BBoundaryBufferingDepth>2</BBoundaryBufferingDepth>
+ <BCreditBuffers>6</BCreditBuffers>
+ <ASlavePortRegister>absent</ASlavePortRegister>
+ <ASlavePortRegisterType>fwd</ASlavePortRegisterType>
+ <AMasterPortRegister>absent</AMasterPortRegister>
+ <AMasterPortRegisterType>fwd</AMasterPortRegisterType>
+ <ABoundaryBuffering>absent</ABoundaryBuffering>
+ <ABoundaryBufferingDepth>2</ABoundaryBufferingDepth>
+ <ACreditBuffers>6</ACreditBuffers>
+ <DSlavePortRegister>absent</DSlavePortRegister>
+ <DSlavePortRegisterType>fwd</DSlavePortRegisterType>
+ <DMasterPortRegister>absent</DMasterPortRegister>
+ <DMasterPortRegisterType>fwd</DMasterPortRegisterType>
+ <DBoundaryBuffering>absent</DBoundaryBuffering>
+ <DBoundaryBufferingDepth>2</DBoundaryBufferingDepth>
+ <DCreditBuffers>6</DCreditBuffers>
+ <FwdChannelPLRegisterSlices>0</FwdChannelPLRegisterSlices>
+ <RevChannelPLRegisterSlices>0</RevChannelPLRegisterSlices>
+ <POWER_DOMAIN_CROSSING>false</POWER_DOMAIN_CROSSING>
+ <HierarchicalClockGating>false</HierarchicalClockGating>
+ <ClockControllerImplementation>asynchronous</ClockControllerImplementation>
+ <QoSEnabled>false</QoSEnabled>
+ <OutputSignals>false</OutputSignals>
+ <QVNEnabled>false</QVNEnabled>
+ <VNExternal>false</VNExternal>
+ <VNExternalBridge>false</VNExternalBridge>
+ <MASTER_PREALLOC_1>false</MASTER_PREALLOC_1>
+ <MASTER_PREALLOC_2>false</MASTER_PREALLOC_2>
+ <MASTER_PREALLOC_3>false</MASTER_PREALLOC_3>
+ <MASTER_PREALLOC_4>false</MASTER_PREALLOC_4>
+ <SLAVE_PREALLOC_1>false</SLAVE_PREALLOC_1>
+ <SLAVE_PREALLOC_2>false</SLAVE_PREALLOC_2>
+ <SLAVE_PREALLOC_3>false</SLAVE_PREALLOC_3>
+ <SLAVE_PREALLOC_4>false</SLAVE_PREALLOC_4>
+ <FW_PHYSICAL_LINK>16</FW_PHYSICAL_LINK>
+ <REV_PHYSICAL_LINK>16</REV_PHYSICAL_LINK>
+ <FW_AXI_SIGNAL>145</FW_AXI_SIGNAL>
+ <REV_AXI_SIGNAL>45</REV_AXI_SIGNAL>
+ <FW_BANDWIDTH_PERCENTAGE>17</FW_BANDWIDTH_PERCENTAGE>
+ <FW_UTILIZATION_PERCENTAGE>86</FW_UTILIZATION_PERCENTAGE>
+ <FW_REDUCTION_PERCENTAGE>91</FW_REDUCTION_PERCENTAGE>
+ <REV_BANDWIDTH_PERCENTAGE>24</REV_BANDWIDTH_PERCENTAGE>
+ <REV_UTILIZATION_PERCENTAGE>98</REV_UTILIZATION_PERCENTAGE>
+ <REV_REDUCTION_PERCENTAGE>78</REV_REDUCTION_PERCENTAGE>
+ <DPEEnabled>false</DPEEnabled>
+ <ParityBitWidth>5</ParityBitWidth>
+ </Parameters>
+ <Domains>
+ <VoltageDomains>
+ <VoltageDomain>
+ <Name>vd0</Name>
+ </VoltageDomain>
+ </VoltageDomains>
+ <PowerDomains>
+ <PowerDomain>
+ <Name>pd0</Name>
+ <PowerDomainType>AlwaysOn</PowerDomainType>
+ <VoltageDomainRef>vd0</VoltageDomainRef>
+ </PowerDomain>
+ </PowerDomains>
+ <ClockDomains>
+ <ClockDomain>
+ <Name>clk_s</Name>
+ <PowerDomainRef>pd0</PowerDomainRef>
+ </ClockDomain>
+ <ClockDomain>
+ <Name>clk_m</Name>
+ <PowerDomainRef>pd0</PowerDomainRef>
+ </ClockDomain>
+ </ClockDomains>
+ <ClockRelations/>
+ <GeographicDomains>
+ <GeographicDomain>
+ <Name>gd0</Name>
+ </GeographicDomain>
+ <GeographicDomain>
+ <Name>gd1</Name>
+ </GeographicDomain>
+ </GeographicDomains>
+ </Domains>
+ <Groups>
+ <ExternalGroups/>
+ </Groups>
+ <Interfaces>
+ <SlaveInterface>
+ <Name>M1_s</Name>
+ <AXISlaveProtocol>
+ <AddressWidth>32</AddressWidth>
+ <DataWidth>32</DataWidth>
+ <ARUSEREnabled>false</ARUSEREnabled>
+ <AWUSEREnabled>false</AWUSEREnabled>
+ <RUSEREnabled>false</RUSEREnabled>
+ <WUSEREnabled>false</WUSEREnabled>
+ <BUSEREnabled>false</BUSEREnabled>
+ </AXISlaveProtocol>
+ <ClockRef>clk_s</ClockRef>
+ </SlaveInterface>
+ <MasterInterface>
+ <Name>M1_m</Name>
+ <AXIMasterProtocol>
+ <AddressWidth>32</AddressWidth>
+ <DataWidth>32</DataWidth>
+ <ARUSEREnabled>false</ARUSEREnabled>
+ <AWUSEREnabled>false</AWUSEREnabled>
+ <RUSEREnabled>false</RUSEREnabled>
+ <WUSEREnabled>false</WUSEREnabled>
+ <BUSEREnabled>false</BUSEREnabled>
+ </AXIMasterProtocol>
+ <ClockRef>clk_m</ClockRef>
+ </MasterInterface>
+ </Interfaces>
+ <MemoryMaps>
+ <MemoryMap>
+ <Name>mm0</Name>
+ <MemoryMapSource>
+ <InterfaceRef>M1_s</InterfaceRef>
+ </MemoryMapSource>
+ <MappedBlock>
+ <InterfaceRef>M1_m</InterfaceRef>
+ <Offset>0</Offset>
+ <Range>4000000000000</Range>
+ </MappedBlock>
+ </MemoryMap>
+ </MemoryMaps>
+ <Paths>
+ <Path>
+ <Source>
+ <InterfaceRef>M1_s</InterfaceRef>
+ </Source>
+ <Targets>
+ <Target>
+ <InterfaceRef>M1_m</InterfaceRef>
+ </Target>
+ </Targets>
+ </Path>
+ </Paths>
+ <VirtualNetworks/>
+ </Specification>
+ <Architecture>
+ <NICConfigFile><?xml version="1.0" encoding="iso-8859-1" ?>
+<periph>
+<product_version_info major_version="00" minor_revision="2" major_revision="1" minor_version="0" part_quality="rel" minor_code="50000" major_group="bu" product_code="nic400_tlx"/>
+<validator_version_info minor_revision="1" major_revision="22" />
+ <global>
+ <qos_status>false</qos_status>
+ <buser_width>0</buser_width>
+ <hcg_en>false</hcg_en>
+ <virtual_networks_status>false</virtual_networks_status>
+ <rsb_arch_central_ring>false</rsb_arch_central_ring>
+ <thin_links_status>true</thin_links_status>
+ <awuser_width>0</awuser_width>
+ <license_status>unlicensed_nic</license_status>
+ <dpe_status>false</dpe_status>
+ <aruser_width>0</aruser_width>
+ <cc_type>async</cc_type>
+ <pl_id_width>4</pl_id_width>
+ <ruser_width>0</ruser_width>
+ <wuser_width>0</wuser_width>
+ </global>
+ <amib>
+ <master_if_port_name>M1_m_m</master_if_port_name>
+ <multi_region>false</multi_region>
+ <tide>0</tide>
+ <tlx>
+ <power_domain_crossing>false</power_domain_crossing>
+ <fwd_tlx>
+ <pl_clock_ratio>1</pl_clock_ratio>
+ <dll_link_user_def_width>8</dll_link_user_def_width>
+ <pl_reg_stages>0</pl_reg_stages>
+ <dll_link_width_option>widest_div_4</dll_link_width_option>
+ </fwd_tlx>
+ <rev_tlx>
+ <pl_clock_ratio>1</pl_clock_ratio>
+ <dll_link_user_def_width>8</dll_link_user_def_width>
+ <pl_reg_stages>0</pl_reg_stages>
+ <dll_link_width_option>widest_div_4</dll_link_width_option>
+ </rev_tlx>
+ <tlx_enable>true</tlx_enable>
+ <ahb_bridge>false</ahb_bridge>
+ <reg>
+ <type>fifo</type>
+ <impl>present</impl>
+ <depth>6</depth>
+ <name>aw</name>
+ <location>boundary</location>
+ </reg>
+ <reg>
+ <type>fifo</type>
+ <impl>present</impl>
+ <depth>6</depth>
+ <name>w</name>
+ <location>boundary</location>
+ </reg>
+ <reg>
+ <type>fifo</type>
+ <impl>present</impl>
+ <depth>6</depth>
+ <name>b</name>
+ <location>boundary</location>
+ </reg>
+ <reg>
+ <type>fifo</type>
+ <impl>present</impl>
+ <depth>6</depth>
+ <name>ar</name>
+ <location>boundary</location>
+ </reg>
+ <reg>
+ <type>fifo</type>
+ <impl>present</impl>
+ <depth>6</depth>
+ <name>r</name>
+ <location>boundary</location>
+ </reg>
+ <reg>
+ <type>fwd</type>
+ <impl>absent</impl>
+ <name>d</name>
+ <location>tlx_fwd</location>
+ </reg>
+ <reg>
+ <type>fwd</type>
+ <impl>absent</impl>
+ <name>d</name>
+ <location>tlx_rev</location>
+ </reg>
+ </tlx>
+ <slave_if_data_width>32</slave_if_data_width>
+ <multi_ported>false</multi_ported>
+ <vn_external>none</vn_external>
+ <vid_width>4</vid_width>
+ <apb_config>false</apb_config>
+ <qv_out>false</qv_out>
+ <master_if_addr_width>32</master_if_addr_width>
+ <clock_domain_name_slave_if>clk_s</clock_domain_name_slave_if>
+ <clock_domain_name_master_if>clk_m</clock_domain_name_master_if>
+ <protocol>axi</protocol>
+ <dest_type>peripheral</dest_type>
+ <name>M1_m</name>
+ <vn_external_bridge>none</vn_external_bridge>
+ <trustzone>nsec</trustzone>
+ <slave_if_port_name>M1_m_s</slave_if_port_name>
+ <clock_boundary>async</clock_boundary>
+ <master_if_data_width>32</master_if_data_width>
+ <reg>
+ <type>rev</type>
+ <impl>present</impl>
+ <name>aw</name>
+ <location>slave_port</location>
+ </reg>
+ <reg>
+ <type>rev</type>
+ <impl>present</impl>
+ <name>w</name>
+ <location>slave_port</location>
+ </reg>
+ <reg>
+ <type>rev</type>
+ <impl>present</impl>
+ <name>ar</name>
+ <location>slave_port</location>
+ </reg>
+ <reg>
+ <type>fwd</type>
+ <impl>absent</impl>
+ <name>b</name>
+ <location>slave_port</location>
+ </reg>
+ <reg>
+ <type>fwd</type>
+ <impl>absent</impl>
+ <name>r</name>
+ <location>slave_port</location>
+ </reg>
+ <reg>
+ <type>fwd</type>
+ <impl>absent</impl>
+ <name>aw</name>
+ <location>master_port</location>
+ </reg>
+ <reg>
+ <type>fwd</type>
+ <impl>absent</impl>
+ <name>w</name>
+ <location>master_port</location>
+ </reg>
+ <reg>
+ <type>fwd</type>
+ <impl>absent</impl>
+ <name>ar</name>
+ <location>master_port</location>
+ </reg>
+ <reg>
+ <type>fwd</type>
+ <impl>absent</impl>
+ <name>b</name>
+ <location>master_port</location>
+ </reg>
+ <reg>
+ <type>fwd</type>
+ <impl>absent</impl>
+ <name>r</name>
+ <location>master_port</location>
+ </reg>
+ </amib>
+ <connect>
+ <ruser>false</ruser>
+ <wuser>false</wuser>
+ <src>M1_m</src>
+ <awuser>false</awuser>
+ <out_trans>16</out_trans>
+ <dest>external</dest>
+ <src_port>M1_m_m</src_port>
+ <protocol>axi</protocol>
+ <buser>false</buser>
+ <out_reads>16</out_reads>
+ <lock>false</lock>
+ <out_writes>16</out_writes>
+ <dest_port>M1_m_m</dest_port>
+ <aruser>false</aruser>
+ </connect>
+ <connect>
+ <ruser>false</ruser>
+ <wuser>false</wuser>
+ <src>external</src>
+ <awuser>false</awuser>
+ <out_trans>32</out_trans>
+ <dest>M1_m</dest>
+ <src_port>M1_m_s</src_port>
+ <protocol>axi</protocol>
+ <buser>false</buser>
+ <out_reads>16</out_reads>
+ <lock>false</lock>
+ <out_writes>16</out_writes>
+ <dest_port>M1_m_s</dest_port>
+ <aruser>false</aruser>
+ </connect>
+</periph>
+</NICConfigFile>
+ </Architecture>
+ <Deliverables>
+ <IPXACT/>
+ <RTL/>
+ <TestBench/>
+ <Reports/>
+ </Deliverables>
+</ConfiguredComponent>
\ No newline at end of file
diff --git a/verif/cocotb/sram_chiplet_cocotb.v b/verif/cocotb/sram_chiplet_cocotb.v
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391