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  • dev
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  • soclabs/nanosoc_tech
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Commits on Source (65)
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with 57 additions and 9292 deletions
# Exclude Simulation Files
# Exclude Compiled Binaries
/software/*/*.elf
/software/*/*.ELF
/software/*/*.hex
/software/*/*.lst
/software/*/*.o
# Compile Test Code Removal
system/testcodes/*/*.elf
system/testcodes/*/*.ELF
system/testcodes/*/*.hex
system/testcodes/*/*.lst
system/testcodes/*/*.o
# Bootrom removal
system/src/bootrom/
# Simulation Removal (If running at Tech Level)
sim
\ No newline at end of file
......@@ -34,24 +34,27 @@ build-job-Z2: # This job runs in the build stage, which runs first.
- cd ../DMA-230_MicroDMA_Controller/
- tar -xf PL230-r0p0-02rel2-1.tar.gz
# move to fpga_imp directory and run the fpga build script for pynq z2
- cd ../../nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/
- if source ./build_fpga_pynq_z2.scr; then
- FILE = ./pynq_export/pz2/pynq/overlays/soclabs/design_1.bit
- if test -f "$FILE"; then
- echo "Build successful"
- else
- echo "Build failed"
- fi
- cd ../../nanosoc/system/fpga_imp/
- source ../../set_env.sh
- mkdir -p $NANOSOC_TECH_DIR/system/src/bootrom
- make -C $NANOSOC_TECH_DIR/system bootrom SIM_TOP_DIR=$NANOSOC_TECH_DIR/sim BOOTROM_BUILD_DIR=$NANOSOC_TECH_DIR/system/src/bootrom TOOL_CHAIN=ds6
- if source ./build_fpga_pynq_z2.scr; then echo "Vivado Finished"; fi
- FILE=./pynq_export/pz2/pynq/overlays/soclabs/design_1.bit
- if test -f "$FILE"; then
- echo "Build successful"
- else
- echo "Build failed"
- exit 1
- fi
# cleanup arm-AAA-ip directory
- cd ../../../../../../
- cd ../../../
- rm -r arm-AAA-ip
artifacts:
paths:
# Keep the generated bit and hwh file from fpga build script
- ./Cortex-M0/nanosoc/systems/mcu/fpga_imp/pynq_export/pz2/pynq/overlays/soclabs/design_1.bit
- ./Cortex-M0/nanosoc/systems/mcu/fpga_imp/pynq_export/pz2/pynq/overlays/soclabs/design_1.hwh
- ./Cortex-M0/nanosoc/systems/mcu/fpga_imp/CI_verification/load_bitfile.py
- ./system/fpga_imp/pynq_export/pz2/pynq/overlays/soclabs/design_1.bit
- ./system/fpga_imp/pynq_export/pz2/pynq/overlays/soclabs/design_1.hwh
- ./system/fpga_imp/CI_verification/load_bitfile.py
tags:
- Vivado2021.1
......@@ -67,24 +70,27 @@ build-job-ZCU104: # This job runs in the build stage, which runs first.
- cd ../DMA-230_MicroDMA_Controller/
- tar -xf PL230-r0p0-02rel2-1.tar.gz
# move to fpga_imp directory and run the fpga build script for pynq z2
- cd ../../nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/
- if source ./build_fpga_pynq_zcu104.scr; then
- FILE = ./pynq_export/pz104/pynq/overlays/soclabs/design_1.bit
- if test -f "$FILE"; then
- echo "Build successful"
- else
- echo "Build failed"
- fi
- cd ../../nanosoc/system/fpga_imp/
- source ../../set_env.sh
- mkdir -p $NANOSOC_TECH_DIR/system/src/bootrom
- make -C $NANOSOC_TECH_DIR/system bootrom SIM_TOP_DIR=$NANOSOC_TECH_DIR/sim BOOTROM_BUILD_DIR=$NANOSOC_TECH_DIR/system/src/bootrom TOOL_CHAIN=ds5
- if source ./build_fpga_pynq_zcu104.scr; then echo "Vivado Finished"; fi
- FILE=./pynq_export/pz104/pynq/overlays/soclabs/design_1.bit
- if test -f "$FILE"; then
- echo "Build successful"
- else
- echo "Build failed"
- exit 1
- fi
# cleanup arm-AAA-ip directory
- cd ../../../../../../
- cd ../../../
- rm -r arm-AAA-ip
artifacts:
paths:
# Keep the generated bit and hwh file from fpga build script
- ./Cortex-M0/nanosoc/systems/mcu/fpga_imp/pynq_export/pz104/pynq/overlays/soclabs/design_1.bit
- ./Cortex-M0/nanosoc/systems/mcu/fpga_imp/pynq_export/pz104/pynq/overlays/soclabs/design_1.hwh
- ./Cortex-M0/nanosoc/systems/mcu/fpga_imp/CI_verification/load_bitfile.py
- ./system/fpga_imp/pynq_export/pz104/pynq/overlays/soclabs/design_1.bit
- ./system/fpga_imp/pynq_export/pz104/pynq/overlays/soclabs/design_1.hwh
- ./system/fpga_imp/CI_verification/load_bitfile.py
tags:
- VLAB-ZCU
......@@ -95,9 +101,9 @@ deploy-job-Z2: # This job runs in the deploy stage.
- echo "Deploying application to Z2"
# use smbclient to transfer accross the bit, hwh and python script files to the z2 xilinx board
# could probably set this up as scp with RSA keys in future
- smbclient //192.168.2.99/xilinx -m SMB3 -U xilinx%xilinx -c 'cd ./pynq/overlays/soclabs/ ; put ./Cortex-M0/nanosoc/systems/mcu/fpga_imp/pynq_export/pz2/pynq/overlays/soclabs/design_1.bit ./design_1.bit'
- smbclient //192.168.2.99/xilinx -m SMB3 -U xilinx%xilinx -c 'cd ./pynq/overlays/soclabs/ ; put ./Cortex-M0/nanosoc/systems/mcu/fpga_imp/pynq_export/pz2/pynq/overlays/soclabs/design_1.hwh ./design_1.hwh'
- cd ./Cortex-M0/nanosoc/systems/mcu/fpga_imp/CI_verification
- smbclient //192.168.2.99/xilinx -m SMB3 -U xilinx%xilinx -c 'cd ./pynq/overlays/soclabs/ ; put ./system/fpga_imp/pynq_export/pz2/pynq/overlays/soclabs/design_1.bit ./design_1.bit'
- smbclient //192.168.2.99/xilinx -m SMB3 -U xilinx%xilinx -c 'cd ./pynq/overlays/soclabs/ ; put ./system/fpga_imp/pynq_export/pz2/pynq/overlays/soclabs/design_1.hwh ./design_1.hwh'
- cd ./system/fpga_imp/CI_verification
- smbclient //192.168.2.99/xilinx -m SMB3 -U xilinx%xilinx -c 'put ./load_bitfile.py ./load_bitfile.py'
# get root access on host machine, this was found to be needed because other screen would not work
# however a more elegant solution would be better
......@@ -148,11 +154,11 @@ deploy-job-ZCU104: # This job runs in the deploy stage.
- screen -r zynq -X stuff "./ZCU104_connect.sh \n"
- sleep 10
# use scp to copy over bit files and python script
- screen -r zynq -X stuff "scp -i ~/.ssh/id_rsa dwn1c21@soclabs.soton.ac.uk:~/builds/wzndG1mA/0/soclabs/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/CI_verification/load_bitfile.py ./ \n"
- screen -r zynq -X stuff "scp -i ~/.ssh/id_rsa dwn1c21@soclabs.soton.ac.uk:~/builds/wzndG1mA/0/soclabs/nanosoc/system/fpga_imp/CI_verification/load_bitfile.py ./ \n"
- sleep 2
- screen -r zynq -X stuff "scp -i ~/.ssh/id_rsa dwn1c21@soclabs.soton.ac.uk:~/builds/wzndG1mA/0/soclabs/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/pynq_export/pz104/pynq/overlays/soclabs/design_1.bit ./pynq/overlays/soclabs/design_1.bit \n"
- screen -r zynq -X stuff "scp -i ~/.ssh/id_rsa dwn1c21@soclabs.soton.ac.uk:~/builds/wzndG1mA/0/soclabs/nanosoc/system/fpga_imp/pynq_export/pz104/pynq/overlays/soclabs/design_1.bit ./pynq/overlays/soclabs/design_1.bit \n"
- sleep 2
- screen -r zynq -X stuff "scp -i ~/.ssh/id_rsa dwn1c21@soclabs.soton.ac.uk:~/builds/wzndG1mA/0/soclabs/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/pynq_export/pz104/pynq/overlays/soclabs/design_1.hwh ./pynq/overlays/soclabs/design_1.hwh \n"
- screen -r zynq -X stuff "scp -i ~/.ssh/id_rsa dwn1c21@soclabs.soton.ac.uk:~/builds/wzndG1mA/0/soclabs/nanosoc/system/fpga_imp/pynq_export/pz104/pynq/overlays/soclabs/design_1.hwh ./pynq/overlays/soclabs/design_1.hwh \n"
- sleep 2
# Need root access to load the overlay onto the FPGA
- screen -r zynq -X stuff "sudo su\n"
......
# rtl_source_soclabs_ip.tcl
#
set iplib_vlog ../../../../../IPLIB
read_verilog $iplib_vlog/FT1248_streamio_v1_0/ft1248_streamio_v1_0.v
read_verilog $iplib_vlog/ADPcontrol_v1_0/ADPcontrol_v1_0.v
read_verilog $iplib_vlog/ADPcontrol_v1_0/ADPmanager.v
export ARM_PRODUCT_PATH=/apps/arm/developmentstudio-2021.0/sw/mappings
export ARM_TOOL_VARIANT=gold
export PATH=$PATH:/apps/arm/developmentstudio-2021.0/sw/ARMCompiler5.06u7/bin/
export ARM_PRODUCT_PATH=/apps/arm/developmentstudio-2021.0/sw/mappings
export ARM_TOOL_VARIANT=gold
export PATH=$PATH:/apps/arm/developmentstudio-2021.0/sw/ARMCompiler5.06u7/bin/
File deleted
//------------------------------------------------------------------------------------
// customised auto-generated synthesizable ROM module abstraction
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// David Flynn (d.w.flynn@soton.ac.uk)
// Date: 2302101100
// Copyright (c) 2021-2, SoC Labs (www.soclabs.org)
//------------------------------------------------------------------------------------
module bootrom (
input wire CLK,
input wire EN,
input wire [9:2] ADDR,
output reg [31:0] RDATA );
reg [9:2] addr_r;
always @(posedge CLK) if (EN) addr_r <= ADDR;
always @(addr_r) case(addr_r[9:2])
8'h00 : RDATA <= 32'h30000368; // 0x0000
8'h01 : RDATA <= 32'h10000335; // 0x0004
8'h02 : RDATA <= 32'h1000033d; // 0x0008
8'h03 : RDATA <= 32'h1000033f; // 0x000c
8'h04 : RDATA <= 32'h00000000; // 0x0010
8'h05 : RDATA <= 32'h00000000; // 0x0014
8'h06 : RDATA <= 32'h00000000; // 0x0018
8'h07 : RDATA <= 32'h00000000; // 0x001c
8'h08 : RDATA <= 32'h00000000; // 0x0020
8'h09 : RDATA <= 32'h00000000; // 0x0024
8'h0a : RDATA <= 32'h00000000; // 0x0028
8'h0b : RDATA <= 32'h10000341; // 0x002c
8'h0c : RDATA <= 32'h00000000; // 0x0030
8'h0d : RDATA <= 32'h00000000; // 0x0034
8'h0e : RDATA <= 32'h10000343; // 0x0038
8'h0f : RDATA <= 32'h10000345; // 0x003c
8'h10 : RDATA <= 32'h10000347; // 0x0040
8'h11 : RDATA <= 32'h10000347; // 0x0044
8'h12 : RDATA <= 32'h10000347; // 0x0048
8'h13 : RDATA <= 32'h10000347; // 0x004c
8'h14 : RDATA <= 32'h10000347; // 0x0050
8'h15 : RDATA <= 32'h10000347; // 0x0054
8'h16 : RDATA <= 32'h10000347; // 0x0058
8'h17 : RDATA <= 32'h10000347; // 0x005c
8'h18 : RDATA <= 32'h10000347; // 0x0060
8'h19 : RDATA <= 32'h10000347; // 0x0064
8'h1a : RDATA <= 32'h10000347; // 0x0068
8'h1b : RDATA <= 32'h00000000; // 0x006c
8'h1c : RDATA <= 32'h10000347; // 0x0070
8'h1d : RDATA <= 32'h10000347; // 0x0074
8'h1e : RDATA <= 32'h10000347; // 0x0078
8'h1f : RDATA <= 32'h10000347; // 0x007c
8'h20 : RDATA <= 32'h10000347; // 0x0080
8'h21 : RDATA <= 32'h10000347; // 0x0084
8'h22 : RDATA <= 32'h10000347; // 0x0088
8'h23 : RDATA <= 32'h10000347; // 0x008c
8'h24 : RDATA <= 32'h10000347; // 0x0090
8'h25 : RDATA <= 32'h10000347; // 0x0094
8'h26 : RDATA <= 32'h10000347; // 0x0098
8'h27 : RDATA <= 32'h10000347; // 0x009c
8'h28 : RDATA <= 32'h10000347; // 0x00a0
8'h29 : RDATA <= 32'h10000347; // 0x00a4
8'h2a : RDATA <= 32'h10000347; // 0x00a8
8'h2b : RDATA <= 32'h10000347; // 0x00ac
8'h2c : RDATA <= 32'h10000347; // 0x00b0
8'h2d : RDATA <= 32'h10000347; // 0x00b4
8'h2e : RDATA <= 32'h10000347; // 0x00b8
8'h2f : RDATA <= 32'h10000347; // 0x00bc
8'h30 : RDATA <= 32'hf802f000; // 0x00c0
8'h31 : RDATA <= 32'hf83ef000; // 0x00c4
8'h32 : RDATA <= 32'hc830a00c; // 0x00c8
8'h33 : RDATA <= 32'h18243808; // 0x00cc
8'h34 : RDATA <= 32'h46a2182d; // 0x00d0
8'h35 : RDATA <= 32'h46ab1e67; // 0x00d4
8'h36 : RDATA <= 32'h465d4654; // 0x00d8
8'h37 : RDATA <= 32'hd10142ac; // 0x00dc
8'h38 : RDATA <= 32'hf830f000; // 0x00e0
8'h39 : RDATA <= 32'h3e0f467e; // 0x00e4
8'h3a : RDATA <= 32'h46b6cc0f; // 0x00e8
8'h3b : RDATA <= 32'h42332601; // 0x00ec
8'h3c : RDATA <= 32'h1afbd000; // 0x00f0
8'h3d : RDATA <= 32'h46ab46a2; // 0x00f4
8'h3e : RDATA <= 32'h47184333; // 0x00f8
8'h3f : RDATA <= 32'h000002dc; // 0x00fc
8'h40 : RDATA <= 32'h000002fc; // 0x0100
8'h41 : RDATA <= 32'hd3023a10; // 0x0104
8'h42 : RDATA <= 32'hc178c878; // 0x0108
8'h43 : RDATA <= 32'h0752d8fa; // 0x010c
8'h44 : RDATA <= 32'hc830d301; // 0x0110
8'h45 : RDATA <= 32'hd501c130; // 0x0114
8'h46 : RDATA <= 32'h600c6804; // 0x0118
8'h47 : RDATA <= 32'h00004770; // 0x011c
8'h48 : RDATA <= 32'h24002300; // 0x0120
8'h49 : RDATA <= 32'h26002500; // 0x0124
8'h4a : RDATA <= 32'hd3013a10; // 0x0128
8'h4b : RDATA <= 32'hd8fbc178; // 0x012c
8'h4c : RDATA <= 32'hd3000752; // 0x0130
8'h4d : RDATA <= 32'hd500c130; // 0x0134
8'h4e : RDATA <= 32'h4770600b; // 0x0138
8'h4f : RDATA <= 32'hbd1fb51f; // 0x013c
8'h50 : RDATA <= 32'hbd10b510; // 0x0140
8'h51 : RDATA <= 32'hf915f000; // 0x0144
8'h52 : RDATA <= 32'hf7ff4611; // 0x0148
8'h53 : RDATA <= 32'hf000fff7; // 0x014c
8'h54 : RDATA <= 32'hf000f868; // 0x0150
8'h55 : RDATA <= 32'hb403f92d; // 0x0154
8'h56 : RDATA <= 32'hfff2f7ff; // 0x0158
8'h57 : RDATA <= 32'hf000bc03; // 0x015c
8'h58 : RDATA <= 32'h0000f933; // 0x0160
8'h59 : RDATA <= 32'h68012000; // 0x0164
8'h5a : RDATA <= 32'h6841468d; // 0x0168
8'h5b : RDATA <= 32'h00004708; // 0x016c
8'h5c : RDATA <= 32'h48532141; // 0x0170
8'h5d : RDATA <= 32'h61010149; // 0x0174
8'h5e : RDATA <= 32'h60812101; // 0x0178
8'h5f : RDATA <= 32'h60814851; // 0x017c
8'h60 : RDATA <= 32'h20204951; // 0x0180
8'h61 : RDATA <= 32'h47706188; // 0x0184
8'h62 : RDATA <= 32'h684a494e; // 0x0188
8'h63 : RDATA <= 32'hd1fc07d2; // 0x018c
8'h64 : RDATA <= 32'h07d2684a; // 0x0190
8'h65 : RDATA <= 32'h6008d100; // 0x0194
8'h66 : RDATA <= 32'h494a4770; // 0x0198
8'h67 : RDATA <= 32'h2b007803; // 0x019c
8'h68 : RDATA <= 32'h684ad009; // 0x01a0
8'h69 : RDATA <= 32'hd1fc07d2; // 0x01a4
8'h6a : RDATA <= 32'h07d2684a; // 0x01a8
8'h6b : RDATA <= 32'h600bd100; // 0x01ac
8'h6c : RDATA <= 32'h2b001c40; // 0x01b0
8'h6d : RDATA <= 32'h4770d1f2; // 0x01b4
8'h6e : RDATA <= 32'h4c44b510; // 0x01b8
8'h6f : RDATA <= 32'h48416821; // 0x01bc
8'h70 : RDATA <= 32'hd00a2900; // 0x01c0
8'h71 : RDATA <= 32'h781aa342; // 0x01c4
8'h72 : RDATA <= 32'hd0212a00; // 0x01c8
8'h73 : RDATA <= 32'h07c96841; // 0x01cc
8'h74 : RDATA <= 32'h6841d1fc; // 0x01d0
8'h75 : RDATA <= 32'hd01707c9; // 0x01d4
8'h76 : RDATA <= 32'ha341e017; // 0x01d8
8'h77 : RDATA <= 32'h2a00781a; // 0x01dc
8'h78 : RDATA <= 32'h6841d009; // 0x01e0
8'h79 : RDATA <= 32'hd1fc07c9; // 0x01e4
8'h7a : RDATA <= 32'h07c96841; // 0x01e8
8'h7b : RDATA <= 32'h6002d100; // 0x01ec
8'h7c : RDATA <= 32'h2a001c5b; // 0x01f0
8'h7d : RDATA <= 32'h2204d1f2; // 0x01f4
8'h7e : RDATA <= 32'h07c96841; // 0x01f8
8'h7f : RDATA <= 32'h6841d1fc; // 0x01fc
8'h80 : RDATA <= 32'hd10007c9; // 0x0200
8'h81 : RDATA <= 32'he7fe6002; // 0x0204
8'h82 : RDATA <= 32'h1c5b6002; // 0x0208
8'h83 : RDATA <= 32'hd1da2a00; // 0x020c
8'h84 : RDATA <= 32'h60202000; // 0x0210
8'h85 : RDATA <= 32'h8f4ff3bf; // 0x0214
8'h86 : RDATA <= 32'h8f6ff3bf; // 0x0218
8'h87 : RDATA <= 32'hffa2f7ff; // 0x021c
8'h88 : RDATA <= 32'hb510bd10; // 0x0220
8'h89 : RDATA <= 32'h48262141; // 0x0224
8'h8a : RDATA <= 32'h61010149; // 0x0228
8'h8b : RDATA <= 32'h60812101; // 0x022c
8'h8c : RDATA <= 32'h60814824; // 0x0230
8'h8d : RDATA <= 32'h21204a24; // 0x0234
8'h8e : RDATA <= 32'ha32f6191; // 0x0238
8'h8f : RDATA <= 32'h2a00781a; // 0x023c
8'h90 : RDATA <= 32'h6841d009; // 0x0240
8'h91 : RDATA <= 32'hd1fc07c9; // 0x0244
8'h92 : RDATA <= 32'h07c96841; // 0x0248
8'h93 : RDATA <= 32'h6002d100; // 0x024c
8'h94 : RDATA <= 32'h2a001c5b; // 0x0250
8'h95 : RDATA <= 32'h4c1dd1f2; // 0x0254
8'h96 : RDATA <= 32'h29006821; // 0x0258
8'h97 : RDATA <= 32'ha31cd00a; // 0x025c
8'h98 : RDATA <= 32'h2a00781a; // 0x0260
8'h99 : RDATA <= 32'h6841d021; // 0x0264
8'h9a : RDATA <= 32'hd1fc07c9; // 0x0268
8'h9b : RDATA <= 32'h07c96841; // 0x026c
8'h9c : RDATA <= 32'he017d017; // 0x0270
8'h9d : RDATA <= 32'h781aa31a; // 0x0274
8'h9e : RDATA <= 32'hd0092a00; // 0x0278
8'h9f : RDATA <= 32'h07c96841; // 0x027c
8'ha0 : RDATA <= 32'h6841d1fc; // 0x0280
8'ha1 : RDATA <= 32'hd10007c9; // 0x0284
8'ha2 : RDATA <= 32'h1c5b6002; // 0x0288
8'ha3 : RDATA <= 32'hd1f22a00; // 0x028c
8'ha4 : RDATA <= 32'h68412204; // 0x0290
8'ha5 : RDATA <= 32'hd1fc07c9; // 0x0294
8'ha6 : RDATA <= 32'h07c96841; // 0x0298
8'ha7 : RDATA <= 32'h6002d100; // 0x029c
8'ha8 : RDATA <= 32'h6002e7fe; // 0x02a0
8'ha9 : RDATA <= 32'h2a001c5b; // 0x02a4
8'haa : RDATA <= 32'h2000d1da; // 0x02a8
8'hab : RDATA <= 32'hf3bf6020; // 0x02ac
8'hac : RDATA <= 32'hf3bf8f4f; // 0x02b0
8'had : RDATA <= 32'hf7ff8f6f; // 0x02b4
8'hae : RDATA <= 32'h2000ff55; // 0x02b8
8'haf : RDATA <= 32'h0000bd10; // 0x02bc
8'hb0 : RDATA <= 32'h40006000; // 0x02c0
8'hb1 : RDATA <= 32'h4000e000; // 0x02c4
8'hb2 : RDATA <= 32'h40011000; // 0x02c8
8'hb3 : RDATA <= 32'h4001f000; // 0x02cc
8'hb4 : RDATA <= 32'h52202a2a; // 0x02d0
8'hb5 : RDATA <= 32'h70616d65; // 0x02d4
8'hb6 : RDATA <= 32'h41523e2d; // 0x02d8
8'hb7 : RDATA <= 32'h000a324d; // 0x02dc
8'hb8 : RDATA <= 32'h72724540; // 0x02e0
8'hb9 : RDATA <= 32'h203a726f; // 0x02e4
8'hba : RDATA <= 32'h414d4552; // 0x02e8
8'hbb : RDATA <= 32'h6c632050; // 0x02ec
8'hbc : RDATA <= 32'h65726165; // 0x02f0
8'hbd : RDATA <= 32'h00000a64; // 0x02f4
8'hbe : RDATA <= 32'h530a0a0a; // 0x02f8
8'hbf : RDATA <= 32'h414c434f; // 0x02fc
8'hc0 : RDATA <= 32'h203a5342; // 0x0300
8'hc1 : RDATA <= 32'h204d5241; // 0x0304
8'hc2 : RDATA <= 32'h74726f43; // 0x0308
8'hc3 : RDATA <= 32'h4d2d7865; // 0x030c
8'hc4 : RDATA <= 32'h616e2030; // 0x0310
8'hc5 : RDATA <= 32'h6f736f6e; // 0x0314
8'hc6 : RDATA <= 32'h00000a63; // 0x0318
8'hc7 : RDATA <= 32'h48034904; // 0x031c
8'hc8 : RDATA <= 32'h47706008; // 0x0320
8'hc9 : RDATA <= 32'h48014902; // 0x0324
8'hca : RDATA <= 32'h47706008; // 0x0328
8'hcb : RDATA <= 32'h05f5e100; // 0x032c
8'hcc : RDATA <= 32'h30000000; // 0x0330
8'hcd : RDATA <= 32'h47804807; // 0x0334
8'hce : RDATA <= 32'h47004807; // 0x0338
8'hcf : RDATA <= 32'he7fee7fe; // 0x033c
8'hd0 : RDATA <= 32'he7fee7fe; // 0x0340
8'hd1 : RDATA <= 32'he7fee7fe; // 0x0344
8'hd2 : RDATA <= 32'h49054804; // 0x0348
8'hd3 : RDATA <= 32'h4b064a05; // 0x034c
8'hd4 : RDATA <= 32'h00004770; // 0x0350
8'hd5 : RDATA <= 32'h10000325; // 0x0354
8'hd6 : RDATA <= 32'h100000c1; // 0x0358
8'hd7 : RDATA <= 32'h30000068; // 0x035c
8'hd8 : RDATA <= 32'h30000368; // 0x0360
8'hd9 : RDATA <= 32'h30000168; // 0x0364
8'hda : RDATA <= 32'h30000168; // 0x0368
8'hdb : RDATA <= 32'h47704770; // 0x036c
8'hdc : RDATA <= 32'h46754770; // 0x0370
8'hdd : RDATA <= 32'hf824f000; // 0x0374
8'hde : RDATA <= 32'h000546ae; // 0x0378
8'hdf : RDATA <= 32'h46534669; // 0x037c
8'he0 : RDATA <= 32'h00c008c0; // 0x0380
8'he1 : RDATA <= 32'hb0184685; // 0x0384
8'he2 : RDATA <= 32'hf7ffb520; // 0x0388
8'he3 : RDATA <= 32'hbc60ffdd; // 0x038c
8'he4 : RDATA <= 32'h08492700; // 0x0390
8'he5 : RDATA <= 32'h260046b6; // 0x0394
8'he6 : RDATA <= 32'hc5c0c5c0; // 0x0398
8'he7 : RDATA <= 32'hc5c0c5c0; // 0x039c
8'he8 : RDATA <= 32'hc5c0c5c0; // 0x03a0
8'he9 : RDATA <= 32'hc5c0c5c0; // 0x03a4
8'hea : RDATA <= 32'h00493d40; // 0x03a8
8'heb : RDATA <= 32'h4770468d; // 0x03ac
8'hec : RDATA <= 32'h4604b510; // 0x03b0
8'hed : RDATA <= 32'h46c046c0; // 0x03b4
8'hee : RDATA <= 32'hf7ff4620; // 0x03b8
8'hef : RDATA <= 32'hbd10fecc; // 0x03bc
8'hf0 : RDATA <= 32'h47704800; // 0x03c0
8'hf1 : RDATA <= 32'h30000004; // 0x03c4
8'hf2 : RDATA <= 32'h20184901; // 0x03c8
8'hf3 : RDATA <= 32'he7febeab; // 0x03cc
8'hf4 : RDATA <= 32'h00020026; // 0x03d0
8'hf5 : RDATA <= 32'h00004770; // 0x03d4
8'hf6 : RDATA <= 32'h100003f8; // 0x03d8
8'hf7 : RDATA <= 32'h30000000; // 0x03dc
8'hf8 : RDATA <= 32'h00000004; // 0x03e0
8'hf9 : RDATA <= 32'h10000104; // 0x03e4
8'hfa : RDATA <= 32'h100003fc; // 0x03e8
8'hfb : RDATA <= 32'h30000004; // 0x03ec
8'hfc : RDATA <= 32'h00000364; // 0x03f0
8'hfd : RDATA <= 32'h10000120; // 0x03f4
8'hfe : RDATA <= 32'h05f5e100; // 0x03f8
8'hff : RDATA <= 32'h00000000; // 0x03fc
default : RDATA <=32'h0;
endcase
endmodule
//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
// (C) COPYRIGHT 2001-2013 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from Arm Limited or its affiliates.
//
// SVN Information
//
// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
//
// Revision : $Revision: 371321 $
//
// Release Information : Cortex-M System Design Kit-r1p1-00rel0
//
//-----------------------------------------------------------------------------
//
//------------------------------------------------------------------------------
// Abstract : AHB BusMatrix top level README file
//------------------------------------------------------------------------------
Introduction
------------
This directory contains the AHB BusMatrix component.
cmsdk_ahb_busmatrix/bin/BuildBusMatrix.pl
The AHB BusMatrix is a configurable component. The configuration
process is handled by a Perl script, located in bin/BuildBusMatrix.pl
cmsdk_ahb_busmatrix/verilog/src
The source code of the configurable AHB Bus matrix is located in
verilog/src directory. Do not use the Verilog files in this directory
directly.
cmsdk_ahb_busmatrix/verilog/built
After configuration process, the Verilog files generated will be stored
in verilog/built directory.
cmsdk_ahb_busmatrix/xml/
During the configuration process, the configuration of the AHB BusMatrix
can be controlled by command line options or by an XML file.
Example XML files can be found in the xml directory.
cmsdk_mtx4x2/verilog/
A preconfigured version of AHB Bus matrix for the example Cortex-M3/M4
system is prepared in the cmsdk_mcu_mtx4x2 directory. The configuration
of this bus matrix can be found in cmsdk_mcu_mtx4x2/xml/
Several example AHB Bus Matrix configuration XML files are provided.
You can generate the AHB bus matrix RTL by running the following command:
> cd logical/cmsdk_ahb_busmatrix
> bin/BuildBusMatrix.pl -xmldir xml -cfg example2x3_full.xml -over -verbose
Please refer to the Cortex-M System Design Kit Technical Reference Manual for
further details on the use of this component.
======================== End of README.txt ===========================
bin/BuildBusMatrix.pl -notimescales -xmldir xml -cfg soclabs_ahb32_4x7.xml -ipxact -ipxactsrcdir=ipxact/src -ipxacttgtdir=ipxact/built -over -verbose >& soclabs_ahb32_4x7.log
//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
// (C) COPYRIGHT 2001-<<copyright_year>> Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from Arm Limited or its affiliates.
//
// SVN Information
//
// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
//
// Revision : $Revision: 371321 $
//
// Release Information : Cortex-M System Design Kit-r1p1-00rel0
//
//-----------------------------------------------------------------------------
//
// -----------------------------------------------------------------------------
// Abstract : Default slave used to drive the slave response signals
// when there are no other slaves selected.
//-----------------------------------------------------------------------------
<<timescale_directive>>
module <<default_slave_name>> (
// Common AHB signals
HCLK,
HRESETn,
// AHB control input signals
HSEL,
HTRANS,
HREADY,
// AHB control output signals
HREADYOUT,
HRESP
);
// -----------------------------------------------------------------------------
// Input and Output declarations
// -----------------------------------------------------------------------------
// Common AHB signals
input HCLK; // AHB System Clock
input HRESETn; // AHB System Reset
// AHB control input signals
input HSEL; // Slave Select
input [1:0] HTRANS; // Transfer type
input HREADY; // Transfer done
// AHB control output signals
output HREADYOUT; // HREADY feedback
output [<<resp>>:0] HRESP; // Transfer response
// -----------------------------------------------------------------------------
// Constant declarations
// -----------------------------------------------------------------------------
// HRESP transfer response signal encoding
`define RSP_OKAY <<resp_v>>'b<<bin_resp_okay>> // OKAY response
`define RSP_ERROR <<resp_v>>'b<<bin_resp_error>> // ERROR response
`define RSP_RETRY <<resp_v>>'b<<bin_resp_retry>> // RETRY response
`define RSP_SPLIT <<resp_v>>'b<<bin_resp_split>> // SPLIT response
//----------------------------- << start excl >> -------------------------------
`define RSP_XFAIL <<resp_v>>'b<<bin_resp_xfail>>; // XFAIL response
//------------------------------ << end excl >> --------------------------------
// -----------------------------------------------------------------------------
// Input and Output declarations
// -----------------------------------------------------------------------------
// Common AHB signals
wire HCLK; // AHB System Clock
wire HRESETn; // AHB System Reset
// AHB control input signals
wire HSEL; // Slave Select
wire [1:0] HTRANS; // Transfer type
wire HREADY; // Transfer done
// AHB control output signals
wire HREADYOUT; // HREADY feedback
wire [<<resp>>:0] HRESP; // Transfer response
// -----------------------------------------------------------------------------
// Signal declarations
// -----------------------------------------------------------------------------
wire invalid; // Set during invalid transfer
wire hready_next; // Controls generation of HREADYOUT output
reg i_hreadyout; // HREADYOUT register
wire [<<resp>>:0] hresp_next; // Generated response
reg [<<resp>>:0] i_hresp; // HRESP register
// -----------------------------------------------------------------------------
// Beginning of main code
// -----------------------------------------------------------------------------
assign invalid = ( HREADY & HSEL & HTRANS[1] );
assign hready_next = i_hreadyout ? ~invalid : 1'b1 ;
assign hresp_next = invalid ? `RSP_ERROR : `RSP_OKAY;
always @(negedge HRESETn or posedge HCLK)
begin : p_resp_seq
if (~HRESETn)
begin
i_hreadyout <= 1'b1;
i_hresp <= `RSP_OKAY;
end
else
begin
i_hreadyout <= hready_next;
if (i_hreadyout)
i_hresp <= hresp_next;
end
end
// Drive outputs with internal versions
assign HREADYOUT = i_hreadyout;
assign HRESP = i_hresp;
endmodule
// --================================= End ===================================--