SOC1-167: ATTEMPT 3

system/fpga_imp/scripts/build_mcu_fpga_ip.tcl

@@ -57,7 +57,7 @@ source scripts/rtl_source_soclabs_ip.tcl
 #source scripts/rtl_source_fpga_ip.tcl
 
 # soclabs modified mcu system 
-set_property verilog_define {NANSOC_EXPANSION_REGION=1} [current_fileset]
+set_property verilog_define {NANOSOC_EXPANSION_REGION=1} [current_fileset]
 
 set soc_vlog ../src
 read_verilog  $soc_vlog/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_busmatrix_default_slave.v