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Commit 4a583970 authored by dam1n19's avatar dam1n19
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SOC1-167: Attempt 5

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system/fpga_imp/scripts/build_mcu_fpga_ip.tcl
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......@@ -88,7 +88,7 @@ read_verilog ../aes/src/soclabs_ahb_aes128_ctrl.v
read_verilog $soc_vlog/verilog/nanosoc_chip.v
read_verilog $soc_vlog/verilog/nanosoc_chip_pads.v
set_property verilog_define {NANOSOC_EXPANSION_REGION=1} [current_fileset]
set_property generic {NANOSOC_EXPANSION_REGION=1} [current_fileset]
set_property top nanosoc_chip [current_fileset]
# FPGA specific timing constraints
......
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