From 4a58397051290db5353b42e078973397b107e687 Mon Sep 17 00:00:00 2001
From: dam1n19 <dam1n19@soton.ac.uk>
Date: Tue, 2 May 2023 14:03:15 +0100
Subject: [PATCH] SOC1-167: Attempt 5
---
system/fpga_imp/scripts/build_mcu_fpga_ip.tcl | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/system/fpga_imp/scripts/build_mcu_fpga_ip.tcl b/system/fpga_imp/scripts/build_mcu_fpga_ip.tcl
index cd2d585..eb8b0e0 100644
--- a/system/fpga_imp/scripts/build_mcu_fpga_ip.tcl
+++ b/system/fpga_imp/scripts/build_mcu_fpga_ip.tcl
@@ -88,7 +88,7 @@ read_verilog ../aes/src/soclabs_ahb_aes128_ctrl.v
read_verilog $soc_vlog/verilog/nanosoc_chip.v
read_verilog $soc_vlog/verilog/nanosoc_chip_pads.v
-set_property verilog_define {NANOSOC_EXPANSION_REGION=1} [current_fileset]
+set_property generic {NANOSOC_EXPANSION_REGION=1} [current_fileset]
set_property top nanosoc_chip [current_fileset]
# FPGA specific timing constraints
--
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