diff --git a/system/fpga_imp/scripts/build_mcu_fpga_ip.tcl b/system/fpga_imp/scripts/build_mcu_fpga_ip.tcl
index cd2d58554c57be892c343623b6ccd290eea7428d..eb8b0e08e7013e0985b93f917026e3b13eb8a6f0 100644
--- a/system/fpga_imp/scripts/build_mcu_fpga_ip.tcl
+++ b/system/fpga_imp/scripts/build_mcu_fpga_ip.tcl
@@ -88,7 +88,7 @@ read_verilog  ../aes/src/soclabs_ahb_aes128_ctrl.v
 read_verilog  $soc_vlog/verilog/nanosoc_chip.v
 read_verilog  $soc_vlog/verilog/nanosoc_chip_pads.v
 
-set_property verilog_define {NANOSOC_EXPANSION_REGION=1} [current_fileset]
+set_property generic {NANOSOC_EXPANSION_REGION=1} [current_fileset]
 set_property top nanosoc_chip [current_fileset]
 
 # FPGA specific timing constraints