SOC1-167: Updated module names to reflect file names

system/test_io/verilog/nanosoc_adp_control_v1_0.v

@@ -6,11 +6,11 @@
 //
 // David Flynn (d.w.flynn@soton.ac.uk)
 //
-// Copyright  2021-2, SoC Labs (www.soclabs.org)
+// Copyright � 2021-2, SoC Labs (www.soclabs.org)
 //-----------------------------------------------------------------------------
 
 
-	module ADPcontrol_v1_0 #
+	module nanosoc_adp_control_v1_0 #
 	(
 		// Users to add parameters here
     parameter PROMPT_CHAR          = "]"

system/test_io/verilog/nanosoc_adp_manager.v

@@ -13,7 +13,7 @@
 //`define ADPBASIC 1
 `begin_keywords "1364-2001"
 
-module ADPmanager // AHB initiator interface
+module nanosoc_adp_manager // AHB initiator interface
    #(parameter PROMPT_CHAR          = "]"
     )
             ( input  wire                  HCLK,

system/verif/verilog/nanosoc_axi_stream_io_8_buffer.v

@@ -14,7 +14,7 @@
 //-----------------------------------------------------------------------------
 
 
-module axi_stream_io_8_buffer
+module nanosoc_axi_stream_io_8_buffer
   (
   input  wire  aclk,
   input  wire  aresetn,

system/verif/verilog/nanosoc_axi_stream_io_8_rxd_to_file.v

@@ -15,7 +15,7 @@
 //-----------------------------------------------------------------------------
 
 
-module axi_stream_io_8_rxd_to_file
+module nanosoc_axi_stream_io_8_rxd_to_file
   #(parameter RXDFILENAME = "rxd.log",
     parameter VERBOSE = 0)
   (

system/verif/verilog/nanosoc_axi_stream_io_8_txd_from_file.v

@@ -15,7 +15,7 @@
 //-----------------------------------------------------------------------------
 
 
-module axi_stream_io_8_txd_from_file
+module nanosoc_axi_stream_io_8_txd_from_file
   #(parameter TXDFILENAME = "txd.cmd",
     parameter VERBOSE = 0)
   (

system/verif/verilog/nanosoc_ft1248x1_track.v

@@ -13,7 +13,7 @@
 // Abstract : FT1248 1-bit data off-chip interface (emulate FT232H device)
 //-----------------------------------------------------------------------------
 
- module ft1248x1_track
+ module nanosoc_ft1248x1_track
   (
   input  wire  ft_clk_i,         // SCLK
   input  wire  ft_ssn_i,         // SS_N

system/verif/verilog/nanosoc_tb.v

 //-----------------------------------------------------------------------------
-// customised example Cortex-M0 controller testbench with CPU trace for RTL or netlist
+// NanoSoC Testbench adpated from example Cortex-M0 controller testbench
 // A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
 //
 // Contributors