diff --git a/system/test_io/verilog/nanosoc_adp_control_v1_0.v b/system/test_io/verilog/nanosoc_adp_control_v1_0.v
index 7b8967c18e34a77bb98084ede844e99853f3e47c..f3dfdcd61d75be530281b95bd752efc5897cc34f 100755
--- a/system/test_io/verilog/nanosoc_adp_control_v1_0.v
+++ b/system/test_io/verilog/nanosoc_adp_control_v1_0.v
@@ -6,11 +6,11 @@
 //
 // David Flynn (d.w.flynn@soton.ac.uk)
 //
-// Copyright � 2021-2, SoC Labs (www.soclabs.org)
+// Copyright � 2021-2, SoC Labs (www.soclabs.org)
 //-----------------------------------------------------------------------------
 
 
-	module ADPcontrol_v1_0 #
+	module nanosoc_adp_control_v1_0 #
 	(
 		// Users to add parameters here
     parameter PROMPT_CHAR          = "]"
diff --git a/system/test_io/verilog/nanosoc_adp_manager.v b/system/test_io/verilog/nanosoc_adp_manager.v
index d536157e632237f992d3e00cacd0d03cc47786eb..827491b5d2752100606980af11aed5eca0745216 100755
--- a/system/test_io/verilog/nanosoc_adp_manager.v
+++ b/system/test_io/verilog/nanosoc_adp_manager.v
@@ -13,7 +13,7 @@
 //`define ADPBASIC 1
 `begin_keywords "1364-2001"
 
-module ADPmanager // AHB initiator interface
+module nanosoc_adp_manager // AHB initiator interface
    #(parameter PROMPT_CHAR          = "]"
     )
             ( input  wire                  HCLK,
diff --git a/system/verif/verilog/nanosoc_axi_stream_io_8_buffer.v b/system/verif/verilog/nanosoc_axi_stream_io_8_buffer.v
index d44280a710518c32f5910e0801820d5b7892b867..6919b49600396fdc8538f8c64405ddfb7eeb192f 100644
--- a/system/verif/verilog/nanosoc_axi_stream_io_8_buffer.v
+++ b/system/verif/verilog/nanosoc_axi_stream_io_8_buffer.v
@@ -14,7 +14,7 @@
 //-----------------------------------------------------------------------------
 
 
-module axi_stream_io_8_buffer
+module nanosoc_axi_stream_io_8_buffer
   (
   input  wire  aclk,
   input  wire  aresetn,
diff --git a/system/verif/verilog/nanosoc_axi_stream_io_8_rxd_to_file.v b/system/verif/verilog/nanosoc_axi_stream_io_8_rxd_to_file.v
index 33b169a5d6a58896af2400a0442562fa85734e19..9c2843183b62c50fc0b89519c7406e8e7437245e 100644
--- a/system/verif/verilog/nanosoc_axi_stream_io_8_rxd_to_file.v
+++ b/system/verif/verilog/nanosoc_axi_stream_io_8_rxd_to_file.v
@@ -15,7 +15,7 @@
 //-----------------------------------------------------------------------------
 
 
-module axi_stream_io_8_rxd_to_file
+module nanosoc_axi_stream_io_8_rxd_to_file
   #(parameter RXDFILENAME = "rxd.log",
     parameter VERBOSE = 0)
   (
diff --git a/system/verif/verilog/nanosoc_axi_stream_io_8_txd_from_file.v b/system/verif/verilog/nanosoc_axi_stream_io_8_txd_from_file.v
index 46307a49f54eeb6321a864867cbd1f46c1278030..9b74cb571264ba8826b4e3db3acabf2bbdd6d4f5 100644
--- a/system/verif/verilog/nanosoc_axi_stream_io_8_txd_from_file.v
+++ b/system/verif/verilog/nanosoc_axi_stream_io_8_txd_from_file.v
@@ -15,7 +15,7 @@
 //-----------------------------------------------------------------------------
 
 
-module axi_stream_io_8_txd_from_file
+module nanosoc_axi_stream_io_8_txd_from_file
   #(parameter TXDFILENAME = "txd.cmd",
     parameter VERBOSE = 0)
   (
diff --git a/system/verif/verilog/nanosoc_ft1248x1_track.v b/system/verif/verilog/nanosoc_ft1248x1_track.v
index ba248f8e48a717c4c9710c60bd20bd4cc6ca98eb..abac373a380463c745443c99bcd5502afa352f20 100644
--- a/system/verif/verilog/nanosoc_ft1248x1_track.v
+++ b/system/verif/verilog/nanosoc_ft1248x1_track.v
@@ -13,7 +13,7 @@
 // Abstract : FT1248 1-bit data off-chip interface (emulate FT232H device)
 //-----------------------------------------------------------------------------
 
- module ft1248x1_track
+ module nanosoc_ft1248x1_track
   (
   input  wire  ft_clk_i,         // SCLK
   input  wire  ft_ssn_i,         // SS_N
diff --git a/system/verif/verilog/nanosoc_tb.v b/system/verif/verilog/nanosoc_tb.v
index 4db768ff2634a4c55b67d0ceb105270431687155..f31b081ddcdbab16df2d8808871742f75e7aa246 100644
--- a/system/verif/verilog/nanosoc_tb.v
+++ b/system/verif/verilog/nanosoc_tb.v
@@ -1,5 +1,5 @@
 //-----------------------------------------------------------------------------
-// customised example Cortex-M0 controller testbench with CPU trace for RTL or netlist
+// NanoSoC Testbench adpated from example Cortex-M0 controller testbench
 // A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
 //
 // Contributors