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Commit 743692b2 authored by dam1n19's avatar dam1n19
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SOC1-167: Restructured simulation makefile further and fixed ft1248 file name bug in nanosoc_chip

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.gitlab-ci.yml
+ 14
− 14
View file @ 743692b2
...@@ -34,7 +34,7 @@ build-job-Z2: # This job runs in the build stage, which runs first. ...@@ -34,7 +34,7 @@ build-job-Z2: # This job runs in the build stage, which runs first.
- cd ../DMA-230_MicroDMA_Controller/ - cd ../DMA-230_MicroDMA_Controller/
- tar -xf PL230-r0p0-02rel2-1.tar.gz - tar -xf PL230-r0p0-02rel2-1.tar.gz
# move to fpga_imp directory and run the fpga build script for pynq z2 # move to fpga_imp directory and run the fpga build script for pynq z2
- cd ../../nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ - cd ../../nanosoc/systems/mcu/fpga_imp/
- if source ./build_fpga_pynq_z2.scr; then echo "Vivado Finished"; fi - if source ./build_fpga_pynq_z2.scr; then echo "Vivado Finished"; fi
- FILE=./pynq_export/pz2/pynq/overlays/soclabs/design_1.bit - FILE=./pynq_export/pz2/pynq/overlays/soclabs/design_1.bit
- if test -f "$FILE"; then - if test -f "$FILE"; then
...@@ -49,9 +49,9 @@ build-job-Z2: # This job runs in the build stage, which runs first. ...@@ -49,9 +49,9 @@ build-job-Z2: # This job runs in the build stage, which runs first.
artifacts: artifacts:
paths: paths:
# Keep the generated bit and hwh file from fpga build script # Keep the generated bit and hwh file from fpga build script
- ./Cortex-M0/nanosoc/systems/mcu/fpga_imp/pynq_export/pz2/pynq/overlays/soclabs/design_1.bit - ./systems/mcu/fpga_imp/pynq_export/pz2/pynq/overlays/soclabs/design_1.bit
- ./Cortex-M0/nanosoc/systems/mcu/fpga_imp/pynq_export/pz2/pynq/overlays/soclabs/design_1.hwh - ./systems/mcu/fpga_imp/pynq_export/pz2/pynq/overlays/soclabs/design_1.hwh
- ./Cortex-M0/nanosoc/systems/mcu/fpga_imp/CI_verification/load_bitfile.py - ./systems/mcu/fpga_imp/CI_verification/load_bitfile.py
tags: tags:
- Vivado2021.1 - Vivado2021.1
...@@ -67,7 +67,7 @@ build-job-ZCU104: # This job runs in the build stage, which runs first. ...@@ -67,7 +67,7 @@ build-job-ZCU104: # This job runs in the build stage, which runs first.
- cd ../DMA-230_MicroDMA_Controller/ - cd ../DMA-230_MicroDMA_Controller/
- tar -xf PL230-r0p0-02rel2-1.tar.gz - tar -xf PL230-r0p0-02rel2-1.tar.gz
# move to fpga_imp directory and run the fpga build script for pynq z2 # move to fpga_imp directory and run the fpga build script for pynq z2
- cd ../../nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ - cd ../../nanosoc/systems/mcu/fpga_imp/
- if source ./build_fpga_pynq_zcu104.scr; then echo "Vivado Finished"; fi - if source ./build_fpga_pynq_zcu104.scr; then echo "Vivado Finished"; fi
- FILE=./pynq_export/pz104/pynq/overlays/soclabs/design_1.bit - FILE=./pynq_export/pz104/pynq/overlays/soclabs/design_1.bit
- if test -f "$FILE"; then - if test -f "$FILE"; then
...@@ -82,9 +82,9 @@ build-job-ZCU104: # This job runs in the build stage, which runs first. ...@@ -82,9 +82,9 @@ build-job-ZCU104: # This job runs in the build stage, which runs first.
artifacts: artifacts:
paths: paths:
# Keep the generated bit and hwh file from fpga build script # Keep the generated bit and hwh file from fpga build script
- ./Cortex-M0/nanosoc/systems/mcu/fpga_imp/pynq_export/pz104/pynq/overlays/soclabs/design_1.bit - ./systems/mcu/fpga_imp/pynq_export/pz104/pynq/overlays/soclabs/design_1.bit
- ./Cortex-M0/nanosoc/systems/mcu/fpga_imp/pynq_export/pz104/pynq/overlays/soclabs/design_1.hwh - ./systems/mcu/fpga_imp/pynq_export/pz104/pynq/overlays/soclabs/design_1.hwh
- ./Cortex-M0/nanosoc/systems/mcu/fpga_imp/CI_verification/load_bitfile.py - ./systems/mcu/fpga_imp/CI_verification/load_bitfile.py
tags: tags:
- VLAB-ZCU - VLAB-ZCU
...@@ -95,9 +95,9 @@ deploy-job-Z2: # This job runs in the deploy stage. ...@@ -95,9 +95,9 @@ deploy-job-Z2: # This job runs in the deploy stage.
- echo "Deploying application to Z2" - echo "Deploying application to Z2"
# use smbclient to transfer accross the bit, hwh and python script files to the z2 xilinx board # use smbclient to transfer accross the bit, hwh and python script files to the z2 xilinx board
# could probably set this up as scp with RSA keys in future # could probably set this up as scp with RSA keys in future
- smbclient //192.168.2.99/xilinx -m SMB3 -U xilinx%xilinx -c 'cd ./pynq/overlays/soclabs/ ; put ./Cortex-M0/nanosoc/systems/mcu/fpga_imp/pynq_export/pz2/pynq/overlays/soclabs/design_1.bit ./design_1.bit' - smbclient //192.168.2.99/xilinx -m SMB3 -U xilinx%xilinx -c 'cd ./pynq/overlays/soclabs/ ; put ./systems/mcu/fpga_imp/pynq_export/pz2/pynq/overlays/soclabs/design_1.bit ./design_1.bit'
- smbclient //192.168.2.99/xilinx -m SMB3 -U xilinx%xilinx -c 'cd ./pynq/overlays/soclabs/ ; put ./Cortex-M0/nanosoc/systems/mcu/fpga_imp/pynq_export/pz2/pynq/overlays/soclabs/design_1.hwh ./design_1.hwh' - smbclient //192.168.2.99/xilinx -m SMB3 -U xilinx%xilinx -c 'cd ./pynq/overlays/soclabs/ ; put ./systems/mcu/fpga_imp/pynq_export/pz2/pynq/overlays/soclabs/design_1.hwh ./design_1.hwh'
- cd ./Cortex-M0/nanosoc/systems/mcu/fpga_imp/CI_verification - cd ./systems/mcu/fpga_imp/CI_verification
- smbclient //192.168.2.99/xilinx -m SMB3 -U xilinx%xilinx -c 'put ./load_bitfile.py ./load_bitfile.py' - smbclient //192.168.2.99/xilinx -m SMB3 -U xilinx%xilinx -c 'put ./load_bitfile.py ./load_bitfile.py'
# get root access on host machine, this was found to be needed because other screen would not work # get root access on host machine, this was found to be needed because other screen would not work
# however a more elegant solution would be better # however a more elegant solution would be better
...@@ -148,11 +148,11 @@ deploy-job-ZCU104: # This job runs in the deploy stage. ...@@ -148,11 +148,11 @@ deploy-job-ZCU104: # This job runs in the deploy stage.
- screen -r zynq -X stuff "./ZCU104_connect.sh \n" - screen -r zynq -X stuff "./ZCU104_connect.sh \n"
- sleep 10 - sleep 10
# use scp to copy over bit files and python script # use scp to copy over bit files and python script
- screen -r zynq -X stuff "scp -i ~/.ssh/id_rsa dwn1c21@soclabs.soton.ac.uk:~/builds/wzndG1mA/0/soclabs/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/CI_verification/load_bitfile.py ./ \n" - screen -r zynq -X stuff "scp -i ~/.ssh/id_rsa dwn1c21@soclabs.soton.ac.uk:~/builds/wzndG1mA/0/soclabs/nanosoc/systems/mcu/fpga_imp/CI_verification/load_bitfile.py ./ \n"
- sleep 2 - sleep 2
- screen -r zynq -X stuff "scp -i ~/.ssh/id_rsa dwn1c21@soclabs.soton.ac.uk:~/builds/wzndG1mA/0/soclabs/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/pynq_export/pz104/pynq/overlays/soclabs/design_1.bit ./pynq/overlays/soclabs/design_1.bit \n" - screen -r zynq -X stuff "scp -i ~/.ssh/id_rsa dwn1c21@soclabs.soton.ac.uk:~/builds/wzndG1mA/0/soclabs/nanosoc/systems/mcu/fpga_imp/pynq_export/pz104/pynq/overlays/soclabs/design_1.bit ./pynq/overlays/soclabs/design_1.bit \n"
- sleep 2 - sleep 2
- screen -r zynq -X stuff "scp -i ~/.ssh/id_rsa dwn1c21@soclabs.soton.ac.uk:~/builds/wzndG1mA/0/soclabs/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/pynq_export/pz104/pynq/overlays/soclabs/design_1.hwh ./pynq/overlays/soclabs/design_1.hwh \n" - screen -r zynq -X stuff "scp -i ~/.ssh/id_rsa dwn1c21@soclabs.soton.ac.uk:~/builds/wzndG1mA/0/soclabs/nanosoc/systems/mcu/fpga_imp/pynq_export/pz104/pynq/overlays/soclabs/design_1.hwh ./pynq/overlays/soclabs/design_1.hwh \n"
- sleep 2 - sleep 2
# Need root access to load the overlay onto the FPGA # Need root access to load the overlay onto the FPGA
- screen -r zynq -X stuff "sudo su\n" - screen -r zynq -X stuff "sudo su\n"
......
systems/mcu/rtl_sim/makefile
+ 64
− 89
View file @ 743692b2
...@@ -36,7 +36,16 @@ ...@@ -36,7 +36,16 @@
#----------------------------------------------------------------------------- #-----------------------------------------------------------------------------
# #
# Configurations # Configurations
#
# Directory of Testcodes
NANOSOC_SYSTEMS_DIR ?= $(NANOSOC_TECH_DIR)/systems
NANOSOC_SW_DIR ?= $(NANOSOC_TECH_DIR)/software
NANOSOC_MCU_DIR := $(NANOSOC_SYSTEMS_DIR)/mcu
VERILOG_DIR := $(NANOSOC_MCU_DIR)/verilog
TESTCODES_DIR := $(NANOSOC_MCU_DIR)/testcodes
RTL_SIM_DIR := $(NANOSOC_MCU_DIR)/rtl_sim
# Name of test directory (e.g. hello, dhry) # Name of test directory (e.g. hello, dhry)
# TESTNAME must be specified on the make command line # TESTNAME must be specified on the make command line
TESTNAME = TESTNAME =
...@@ -51,56 +60,15 @@ TEST_LIST = hello dhry sleep_demo interrupt_demo dualtimer_demo \ ...@@ -51,56 +60,15 @@ TEST_LIST = hello dhry sleep_demo interrupt_demo dualtimer_demo \
# Default to DS-5 tool-chain # Default to DS-5 tool-chain
TOOL_CHAIN = ds5 TOOL_CHAIN = ds5
# Choose the core instantiated, can be either # Select System Components (Set here but not currently used)
# - CORTEX_M0PLUS (Cortex-M0+) CPU_PRODUCT ?= CORTEX_M0
# - CORTEX_M0 (Cortex-M0) DMA_PRODUCT ?= DMA_230
# - CORTEX_M0_DS (Cortex-M0 DesignStart version)
# Note: for all processors, make sure that the __MPU_PRESENT variable in the header file agrees with the setting made in
# the processor configuration (refer to Section 4.3.3 of the Example System Guide). The header file is either:
# ../../../software/cmsis/Device/ARM/CMSDK_CM0/Include/CMSDK_CM0.h
# or
# ../../../software/cmsis/Device/ARM/CMSDK_CM0plus/Include/CMSDK_CM0plus.h
# to match the CPU_PRODUCT selected
# Note: for the M0+ processor, make sure that the __VTOR_PRESENT variable in the header file agrees with the setting made in
# the processor configuration (refer to Section 4.3.3 of the Example System Guide). The header file is:
# ../../../software/cmsis/Device/ARM/CMSDK_CM0plus/Include/CMSDK_CM0plus.h
#DF#CPU_PRODUCT = CORTEX_M0PLUS
CPU_PRODUCT = CORTEX_M0
DMA_PRODUCT = DMA_230
# Select Verilog Command File based on CPU type
ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
# For Cortex-M0+ product users
TBENCH_VC = ../verilog/tbench_M0P.vc
endif
# Select Verilog Command File based on CPU type
ifeq ($(CPU_PRODUCT),CORTEX_M0)
# For Cortex-M0 product users
# TBENCH_VC += -f $(PROJECT_DIR)/flist/cortex-m0/cortex-m0_ip.flist
DEFINES_VC = +define+CORTEX_M0 +define+USE_TARMAC
endif
ifeq ($(CPU_PRODUCT),CORTEX_M0_DS)
# For Cortex-M0 DesignStart users
TBENCH_VC = ../verilog/tbench_M0_DS.vc
endif
ifeq ($(DMA_PRODUCT),DMA_230)
# For Cortex-M0 product users
# TBENCH_VC += -f $(PROJECT_DIR)/flist/dma-230/pl230_ip.flist
endif
TBENCH_VC += -f $(PROJECT_DIR)/flist/project/system.flist # Simulator Defines
ACCELERATOR_VC = DEFINES_VC += +define+CORTEX_M0 +define+USE_TARMAC
# ACCELERATOR_IP = SHA_2 # Simulator Command file to specify RTL source files
TBENCH_VC ?= -f $(PROJECT_DIR)/flist/project/system.flist
# ifeq ($(ACCELERATOR_IP),SHA_2)
# # For SHA2 Accelerator IP
# ACCELERATOR_VC = -sv -f $(SOC_TOP_DIR)/sha-2-accelerator/flist/sha-2-accelerator_src.flist
# ACCELERATOR_VC += -f $(SOC_TOP_DIR)/accelerator-wrapper/flist/accelerator-wrapper_src.flist
# endif
#ADP command File #ADP command File
# ADP_FILE ?= $(SOC_TOP_DIR)/accelerator-wrapper/simulate/stimulus/adp_hash_stim.cmd # ADP_FILE ?= $(SOC_TOP_DIR)/accelerator-wrapper/simulate/stimulus/adp_hash_stim.cmd
...@@ -111,6 +79,13 @@ ADP_OPTIONS := -define ADP_FILE=\"$(ADP_PATH)\" ...@@ -111,6 +79,13 @@ ADP_OPTIONS := -define ADP_FILE=\"$(ADP_PATH)\"
# Simulator type (mti/vcs/xm) # Simulator type (mti/vcs/xm)
SIMULATOR = xm SIMULATOR = xm
# Directory to put simulation files
SIM_DIR ?=
ifeq ($(SIM_DIR),)
SIM_DIR := .
endif
# MTI option # MTI option
#DF#MTI_OPTIONS = -novopt #DF#MTI_OPTIONS = -novopt
MTI_OPTIONS = -suppress 2892 MTI_OPTIONS = -suppress 2892
...@@ -123,7 +98,7 @@ VCS_VC_OPTIONS = -f $(TBENCH_VC) $(ACCELERATOR_VC) ...@@ -123,7 +98,7 @@ VCS_VC_OPTIONS = -f $(TBENCH_VC) $(ACCELERATOR_VC)
# XM verilog option # XM verilog option
XMSIM_OPTIONS = -unbuffered -status -LICQUEUE -f xmsim.args -cdslib cds.lib -hdlvar hdl.var -NBASYNC XMSIM_OPTIONS = -unbuffered -status -LICQUEUE -f xmsim.args -cdslib cds.lib -hdlvar hdl.var -NBASYNC
XM_VC_OPTIONS = $(TBENCH_VC) $(ACCELERATOR_VC) $(ADP_OPTIONS) XM_VC_OPTIONS = $(TBENCH_VC) $(ACCELERATOR_VC) $(ADP_OPTIONS)
# Boot Loader image # Boot Loader image
BOOTLOADER = bootloader BOOTLOADER = bootloader
...@@ -191,32 +166,32 @@ all_vcs : compile_vcs bootrom debugtester ...@@ -191,32 +166,32 @@ all_vcs : compile_vcs bootrom debugtester
compile_xm : compile_xm :
@echo ADP_FILE @echo ADP_FILE
@echo $(ADP_OPTIONS) @echo $(ADP_OPTIONS)
xmprep +overwrite $(XM_VC_OPTIONS) $(DEFINES_VC) +debug -timescale 1ps/1ps -top tb_nanosoc | tee compile_xm.log cd $(SIM_DIR); xmprep +overwrite $(XM_VC_OPTIONS) $(DEFINES_VC) +debug -timescale 1ps/1ps -top tb_nanosoc | tee compile_xm.log
xmvlog -work worklib -f xmvlog_sv.args -f xmvlog_ver.args -sv | tee -a compile_xm.log cd $(SIM_DIR); xmvlog -work worklib -f xmvlog_sv.args -f xmvlog_ver.args -sv | tee -a compile_xm.log
xmelab -mess -f xmelab.args -access +r | tee -a compile_xm.log cd $(SIM_DIR); xmelab -mess -f xmelab.args -access +r | tee -a compile_xm.log
# Note : If coverage is required, you can add -coverage all to xmelab # Note : If coverage is required, you can add -coverage all to xmelab
# Run simulation in batch mode # Run simulation in batch mode
run_xm : code compile_xm run_xm : code compile_xm
@if [ ! -d logs ] ; then \ @if [ ! -d logs ] ; then \
mkdir logs; \ mkdir $(SIM_DIR)/logs; \
fi fi
@echo run > run.tcl.tmp @echo run > run.tcl.tmp
@echo exit >> run.tcl.tmp @echo exit >> run.tcl.tmp
@mv run.tcl.tmp run.tcl @mv $(SIM_DIR)/run.tcl.tmp $(SIM_DIR)/run.tcl
xmsim $(XMSIM_OPTIONS) -input run.tcl | tee logs/run_$(TESTNAME).log ; cd $(SIM_DIR); xmsim $(XMSIM_OPTIONS) -input run.tcl | tee logs/run_$(TESTNAME).log ;
# @make verify # @make verify
# Run simulation in interactive mode # Run simulation in interactive mode
sim_xm : code compile_xm sim_xm : code compile_xm
xmsim -gui $(XMSIM_OPTIONS) cd $(SIM_DIR); xmsim -gui $(XMSIM_OPTIONS)
@make verify # @make verify
# Compile RTL, and run all tests in batch mode # Compile RTL, and run all tests in batch mode
all_xm : compile_xm bootrom debugtester all_xm : compile_xm bootrom debugtester
@if [ ! -d logs ] ; then \ @if [ ! -d $(SIM_DIR)/logs ] ; then \
mkdir logs; \ mkdir $(SIM_DIR)/logs; \
fi fi
@echo run > run.tcl.tmp @echo run > run.tcl.tmp
@echo exit >> run.tcl.tmp @echo exit >> run.tcl.tmp
...@@ -286,13 +261,13 @@ code : testcode bootrom debugtester ...@@ -286,13 +261,13 @@ code : testcode bootrom debugtester
# Compile bootloader # Compile bootloader
# Note : The use of ls after compile allows the computing server to sync up # Note : The use of ls after compile allows the computing server to sync up
bootrom: bootrom:
@(cd ../testcodes/$(BOOTLOADER) ;\ @(cd $(NANOSOC_MCU_DIR)/$(BOOTLOADER) ;\
make all $(SW_MAKE_OPTIONS) ;\ make all $(SW_MAKE_OPTIONS) ;\
echo Compile done ;\ echo Compile done ;\
ls > /dev/null ;\ ls > /dev/null ;\
echo Copy $(BOOTLOADER).hex ;\ echo Copy $(BOOTLOADER).hex ;\
if [ -e $(BOOTLOADER).hex ] ; then \ if [ -e $(BOOTLOADER).hex ] ; then \
cp $(BOOTLOADER).hex ../../rtl_sim/$(BOOTLOADER).hex ;\ cp $(BOOTLOADER).hex $(RTL_SIM_DIR)/$(BOOTLOADER).hex ;\
else \ else \
while [ ! -e $(BOOTLOADER).hex ] ; do \ while [ ! -e $(BOOTLOADER).hex ] ; do \
echo Wait for hex file ...; \ echo Wait for hex file ...; \
...@@ -300,14 +275,14 @@ bootrom: ...@@ -300,14 +275,14 @@ bootrom:
sleep 5; \ sleep 5; \
done; \ done; \
if [ -e $(BOOTLOADER).hex ] ; then \ if [ -e $(BOOTLOADER).hex ] ; then \
cp $(BOOTLOADER).hex ../../rtl_sim/$(BOOTLOADER).hex ;\ cp $(BOOTLOADER).hex $(RTL_SIM_DIR)/$(BOOTLOADER).hex ;\
else \ else \
echo Problem reading hex file ;\ echo Problem reading hex file ;\
exit 1; \ exit 1; \
fi ;\ fi ;\
fi ;\ fi ;\
cp $(BOOTLOADER).hex ../../rtl_sim/$(BOOTLOADER).hex ;\ cp $(BOOTLOADER).hex $(RTL_SIM_DIR)/$(BOOTLOADER).hex ;\
cd ../../rtl_sim ) cd $(RTL_SIM_DIR) )
# Compile test code # Compile test code
# Note : The use of ls after compile allows the computing server to sync up # Note : The use of ls after compile allows the computing server to sync up
...@@ -315,14 +290,14 @@ testcode: ...@@ -315,14 +290,14 @@ testcode:
ifeq ($(TESTNAME),) ifeq ($(TESTNAME),)
$(error Please specify TESTNAME on the make command line) $(error Please specify TESTNAME on the make command line)
endif endif
@(if [ -d "../testcodes/$(TESTNAME)" ] ; then \ @(if [ -d "$(TESTCODES_DIR)/$(TESTNAME)" ] ; then \
cd ../testcodes/$(TESTNAME) ;\ cd $(TESTCODES_DIR)/$(TESTNAME) ;\
make all $(SW_MAKE_OPTIONS) ; \ make all $(SW_MAKE_OPTIONS) ; \
echo Compile done ;\ echo Compile done ;\
ls > /dev/null ;\ ls > /dev/null ;\
echo Copy $(TESTNAME).hex ;\ echo Copy $(TESTNAME).hex ;\
if [ -e $(TESTNAME).hex ] ; then \ if [ -e $(TESTNAME).hex ] ; then \
cp $(TESTNAME).hex ../../rtl_sim/image.hex ; \ cp $(TESTNAME).hex $(RTL_SIM_DIR)/image.hex ; \
else \ else \
while [ ! -e $(TESTNAME).hex ] ; do \ while [ ! -e $(TESTNAME).hex ] ; do \
echo Wait for $(TESTNAME).hex file ...; \ echo Wait for $(TESTNAME).hex file ...; \
...@@ -330,13 +305,13 @@ endif ...@@ -330,13 +305,13 @@ endif
sleep 5 ; \ sleep 5 ; \
done; \ done; \
if [ -e $(TESTNAME).hex ] ; then \ if [ -e $(TESTNAME).hex ] ; then \
cp $(TESTNAME).hex ../../rtl_sim/image.hex ; \ cp $(TESTNAME).hex $(RTL_SIM_DIR)/image.hex ; \
else \ else \
echo Problem reading hex file ;\ echo Problem reading hex file ;\
exit 1; \ exit 1; \
fi ;\ fi ;\
fi ;\ fi ;\
cd ../../rtl_sim ;\ cd $(RTL_SIM_DIR) ;\
else \ else \
echo "ERROR: invalid TESTNAME value ( $(TESTNAME) )" ;\ echo "ERROR: invalid TESTNAME value ( $(TESTNAME) )" ;\
exit 1 ;\ exit 1 ;\
...@@ -347,13 +322,13 @@ endif ...@@ -347,13 +322,13 @@ endif
# Compile debugtester # Compile debugtester
# Note : The use of ls after compile allows the computing server to sync up # Note : The use of ls after compile allows the computing server to sync up
debugtester: debugtester:
@(cd ../../../software/debug_tester ;\ @(cd $(NANOSOC_SW_DIR)/debug_tester ;\
make all $(SW_MAKE_OPTIONS) ;\ make all $(SW_MAKE_OPTIONS) ;\
echo Compile done ;\ echo Compile done ;\
ls > /dev/null ;\ ls > /dev/null ;\
echo Copy $(DEBUGTESTER)_le.hex ;\ echo Copy $(DEBUGTESTER)_le.hex ;\
if [ -e $(DEBUGTESTER)_le.hex ] ; then \ if [ -e $(DEBUGTESTER)_le.hex ] ; then \
cp $(DEBUGTESTER)_le.hex ../../systems/mcu/rtl_sim/$(DEBUGTESTER)_le.hex ;\ cp $(DEBUGTESTER)_le.hex $(RTL_SIM_DIR)/$(DEBUGTESTER)_le.hex ;\
else \ else \
while [ ! -e $(DEBUGTESTER)_le.hex ] ; do \ while [ ! -e $(DEBUGTESTER)_le.hex ] ; do \
echo Wait for hex file ...; \ echo Wait for hex file ...; \
...@@ -361,12 +336,12 @@ debugtester: ...@@ -361,12 +336,12 @@ debugtester:
sleep 5 ; \ sleep 5 ; \
done; \ done; \
if [ -e $(DEBUGTESTER)_le.hex ] ; then \ if [ -e $(DEBUGTESTER)_le.hex ] ; then \
cp $(DEBUGTESTER)_le.hex ../../systems/mcu/rtl_sim/$(DEBUGTESTER)_le.hex ;\ cp $(DEBUGTESTER)_le.hex $(RTL_SIM_DIR)/$(DEBUGTESTER)_le.hex ;\
fi ;\ fi ;\
fi ;\ fi ;\
echo Copy $(DEBUGTESTER)_be.hex ;\ echo Copy $(DEBUGTESTER)_be.hex ;\
if [ -e $(DEBUGTESTER)_be.hex ] ; then \ if [ -e $(DEBUGTESTER)_be.hex ] ; then \
cp $(DEBUGTESTER)_be.hex ../../systems/mcu/rtl_sim/$(DEBUGTESTER)_be.hex ;\ cp $(DEBUGTESTER)_be.hex $(RTL_SIM_DIR)/$(DEBUGTESTER)_be.hex ;\
else \ else \
while [ ! -e $(DEBUGTESTER)_be.hex ] ; do \ while [ ! -e $(DEBUGTESTER)_be.hex ] ; do \
echo Wait for hex file ...;\ echo Wait for hex file ...;\
...@@ -374,14 +349,14 @@ debugtester: ...@@ -374,14 +349,14 @@ debugtester:
sleep 5 ; \ sleep 5 ; \
done; \ done; \
if [ -e $(DEBUGTESTER)_be.hex ] ; then \ if [ -e $(DEBUGTESTER)_be.hex ] ; then \
cp $(DEBUGTESTER)_be.hex ../../systems/mcu/rtl_sim/$(DEBUGTESTER)_be.hex ;\ cp $(DEBUGTESTER)_be.hex $(RTL_SIM_DIR)/$(DEBUGTESTER)_be.hex ;\
fi ;\ fi ;\
fi ;\ fi ;\
if [ ! -e $(DEBUGTESTER)_le.hex ] && [ ! -e $(DEBUGTESTER)_be.hex ] ; then \ if [ ! -e $(DEBUGTESTER)_le.hex ] && [ ! -e $(DEBUGTESTER)_be.hex ] ; then \
echo Problem reading hex file ;\ echo Problem reading hex file ;\
exit 1 ;\ exit 1 ;\
fi ;\ fi ;\
cd ../../systems/mcu/rtl_sim ) cd $(RTL_SIM_DIR) )
# Compile all software including boot ROM # Compile all software including boot ROM
compile_all_code: bootrom debugtester compile_all_code: bootrom debugtester
...@@ -402,37 +377,37 @@ compile_all_code: bootrom debugtester ...@@ -402,37 +377,37 @@ compile_all_code: bootrom debugtester
# #
# rm -Rf * # rm -Rf *
# ../tools/v2html -f ../verilog/v2html_M0.vc -ht cmsdk_mcu_system # ../tools/v2html -f $(VERILOG_DIR)/v2html_M0.vc -ht cmsdk_mcu_system
# cp -p tb_cmsdk_mcu.v.html hierarchy.html # cp -p tb_cmsdk_mcu.v.html hierarchy.html
v2html: v2html:
echo building HTML tree echo building HTML tree
@if [ ! -d ../v2html_doc ] ; then \ @if [ ! -d $(NANOSOC_MCU_DIR)/v2html_doc ] ; then \
mkdir ../v2html_doc; \ mkdir $(NANOSOC_MCU_DIR)/v2html_doc; \
fi fi
@(cd ../v2html_doc; \ @(cd $(NANOSOC_MCU_DIR)/v2html_doc; \
rm *.html; rm *.gif; rm *.gz; \ rm *.html; rm *.gif; rm *.gz; \
~/tools/v2html -f ../verilog/v2html_M0.vc -ht nanosoc_chip ; \ ~/tools/v2html -f $(VERILOG_DIR)/v2html_M0.vc -ht nanosoc_chip ; \
cp -p tb_nanosoc.v.html hierarchy.html ; \ cp -p tb_nanosoc.v.html hierarchy.html ; \
cd ../rtl_sim ; ) cd $(RTL_SIM_DIR) ; )
gtar zcvf ../v2html_doc.tgz ../v2html_doc gtar zcvf $(NANOSOC_MCU_DIR)/v2html_doc.tgz $(NANOSOC_MCU_DIR)/v2html_doc
# Remove all software compilation results # Remove all software compilation results
clean_all_code: clean_all_code:
@(cd ../../../software/debug_tester ; make clean; cd ../../systems/mcu/rtl_sim; ) @(cd $(NANOSOC_SW_DIR)/debug_tester ; make clean; cd $(RTL_SIM_DIR); )
@(cd ../testcodes/$(BOOTLOADER) ; make clean; cd ../../rtl_sim; ) @(cd $(TESTCODES_DIR)/$(BOOTLOADER) ; make clean; cd $(RTL_SIM_DIR); )
for thistest in $(TEST_LIST) ; do \ for thistest in $(TEST_LIST) ; do \
echo Cleaning $$thistest ... ; \ echo Cleaning $$thistest ... ; \
cd ../testcodes/$$thistest ; \ cd $(TESTCODES_DIR)/$$thistest ; \
make clean; \ make clean; \
cd ../../rtl_sim; \ cd $(RTL_SIM_DIR); \
done done
# Remove only bootloader and default selected test # Remove only bootloader and default selected test
clean_code: clean_code:
@(cd ../testcodes/$(BOOTLOADER) ; make clean; cd ../../rtl_sim; ) @(cd $(TESTCODES_DIR)/$(BOOTLOADER) ; make clean; cd $(RTL_SIM_DIR); )
@(cd ../testcodes/$(TESTNAME) ; make clean; cd ../../rtl_sim; ) @(cd $(TESTCODES_DIR)/$(TESTNAME) ; make clean; cd $(RTL_SIM_DIR); )
# ----- verification ------ # ----- verification ------
verify: verify:
......
systems/mcu/verilog/nanosoc_chip.v
+ 1
− 1
View file @ 743692b2
...@@ -1252,7 +1252,7 @@ localparam AWRAM9 = ADDR_WIDTH_RAM; // Address width - to match RAM instance siz ...@@ -1252,7 +1252,7 @@ localparam AWRAM9 = ADDR_WIDTH_RAM; // Address width - to match RAM instance siz
wire [7:0] ft_clkdiv = 8'd03; wire [7:0] ft_clkdiv = 8'd03;
ft1248_streamio_v1_0 # ft1248_stream_io_v1_0 #
(.FT1248_WIDTH (1), (.FT1248_WIDTH (1),
.FT1248_CLKON(0) ) .FT1248_CLKON(0) )
u_ftdio_com ( u_ftdio_com (
......
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