SOC1-167: Updated design and verif references to updated module names
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- system/makefile 2 additions, 2 deletionssystem/makefile
- system/src/verilog/nanosoc_chip.v 5 additions, 5 deletionssystem/src/verilog/nanosoc_chip.v
- system/src/verilog/nanosoc_sysio.v 1 addition, 1 deletionsystem/src/verilog/nanosoc_sysio.v
- system/test_io/verilog/nanosoc_adp_control_v1_0.v 2 additions, 2 deletionssystem/test_io/verilog/nanosoc_adp_control_v1_0.v
- system/verif/verilog/nanosoc_tb.v 19 additions, 19 deletionssystem/verif/verilog/nanosoc_tb.v
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