From a0ac6688b4031dbd37877c2a665e4e375d918cbc Mon Sep 17 00:00:00 2001
From: dam1n19 <dam1n19@soton.ac.uk>
Date: Fri, 28 Apr 2023 20:12:03 +0100
Subject: [PATCH] SOC1-167: Updated design and verif references to updated
module names
---
system/makefile | 4 +-
system/src/verilog/nanosoc_chip.v | 10 ++---
system/src/verilog/nanosoc_sysio.v | 2 +-
.../verilog/nanosoc_adp_control_v1_0.v | 4 +-
system/verif/verilog/nanosoc_tb.v | 38 +++++++++----------
5 files changed, 29 insertions(+), 29 deletions(-)
diff --git a/system/makefile b/system/makefile
index 59eaff5..bd86b5b 100644
--- a/system/makefile
+++ b/system/makefile
@@ -165,7 +165,7 @@ all_vcs : compile_vcs bootrom debugtester
compile_xm :
@echo ADP_FILE
@echo $(ADP_OPTIONS)
- cd $(SIM_DIR); xmprep +overwrite $(XM_VC_OPTIONS) $(DEFINES_VC) +debug -timescale 1ps/1ps -top tb_nanosoc | tee compile_xm.log
+ cd $(SIM_DIR); xmprep +overwrite $(XM_VC_OPTIONS) $(DEFINES_VC) +debug -timescale 1ps/1ps -top nanosoc_tb | tee compile_xm.log
cd $(SIM_DIR); xmvlog -work worklib -f xmvlog_sv.args -f xmvlog_ver.args -sv | tee -a compile_xm.log
cd $(SIM_DIR); xmelab -mess -f xmelab.args -access +r | tee -a compile_xm.log
@@ -387,7 +387,7 @@ v2html:
@(cd $(NANOSOC_HTML_DIR)/build; \
rm *.html; rm *.gif; rm *.gz; \
~/tools/v2html -f $(VERILOG_DIR)/v2html_M0.vc -ht nanosoc_chip ; \
- cp -p tb_nanosoc.v.html hierarchy.html ; \
+ cp -p nanosoc_tb.v.html hierarchy.html ; \
cd $(SIM_DIR) ; )
gtar zcvf $(NANOSOC_HTML_DIR)/v2html_doc.tgz $(NANOSOC_HTML_DIR)/build
diff --git a/system/src/verilog/nanosoc_chip.v b/system/src/verilog/nanosoc_chip.v
index 3da5bf3..fe424b4 100644
--- a/system/src/verilog/nanosoc_chip.v
+++ b/system/src/verilog/nanosoc_chip.v
@@ -623,8 +623,8 @@ localparam CORTEX_M0 = 1;
//------------------------------------------------------------------------------
// BusMatrix instance
- soclabs_4x7_AhbMatrix_lite
- u_soclabs_4x7_AhbMatrix_lite (
+ nanosoc_ahb32_4x7_busmatrix_lite
+ u_nanosoc_ahb32_4x7_busmatrix_lite (
.HCLK (HCLK),
.HRESETn (HRESETn),
.REMAP (REMAP),
@@ -913,7 +913,7 @@ nanosoc_exp #(.ADDRWIDTH(29)
// mapped 0x00000000-0x0000ffff
//----------------------------------------
-ahb_bootrom
+nanosoc_ahb_bootrom
// #(.AW(10) ) // 1K bytes ROM
u_ahb_bootloader (
.HCLK (HCLK),
@@ -1183,7 +1183,7 @@ localparam AWRAM9 = ADDR_WIDTH_RAM; // Address width - to match RAM instance siz
assign ADPRESETREQ = adp_gpo8[0];
// ADP debug controller present
- ADPcontrol_v1_0 u_ADP (
+ nanosoc_adp_control_v1_0 u_adp_control (
// Clock and Reset
.ahb_hclk (HCLK),
.ahb_hresetn (HRESETn),
@@ -1252,7 +1252,7 @@ localparam AWRAM9 = ADDR_WIDTH_RAM; // Address width - to match RAM instance siz
wire [7:0] ft_clkdiv = 8'd03;
- ft1248_stream_io_v1_0 #
+ nanosoc_ft1248_stream_io_v1_0 #
(.FT1248_WIDTH (1),
.FT1248_CLKON(0) )
u_ftdio_com (
diff --git a/system/src/verilog/nanosoc_sysio.v b/system/src/verilog/nanosoc_sysio.v
index c6a271c..46395db 100644
--- a/system/src/verilog/nanosoc_sysio.v
+++ b/system/src/verilog/nanosoc_sysio.v
@@ -413,7 +413,7 @@ module nanosoc_sysio
.INCLUDE_APB_WATCHDOG (1), // Include APB watchdog module
.BE (BE)
)
- u_apb_subsystem(
+ u_nanosoc_apb_subsystem(
// AHB interface for AHB to APB bridge
.HCLK (HCLK),
diff --git a/system/test_io/verilog/nanosoc_adp_control_v1_0.v b/system/test_io/verilog/nanosoc_adp_control_v1_0.v
index f3dfdcd..81a3da2 100755
--- a/system/test_io/verilog/nanosoc_adp_control_v1_0.v
+++ b/system/test_io/verilog/nanosoc_adp_control_v1_0.v
@@ -66,9 +66,9 @@
// Add user logic here
-ADPmanager
+nanosoc_adp_manager
#(.PROMPT_CHAR (PROMPT_CHAR))
- ADPmanager(
+ u_adp_manager(
.HCLK (ahb_hclk ),
.HRESETn (ahb_hresetn ),
.HADDR32_o (ahb_haddr ),
diff --git a/system/verif/verilog/nanosoc_tb.v b/system/verif/verilog/nanosoc_tb.v
index f31b081..80af5ab 100644
--- a/system/verif/verilog/nanosoc_tb.v
+++ b/system/verif/verilog/nanosoc_tb.v
@@ -229,8 +229,8 @@ reg baud_clk_del;
wire uart_clk = (FASTMODE) ? PCLK : baud_clk; //(baud_clk & !baud_clk_del);
- cmsdk_uart_capture #(.LOGFILENAME("uart2.log"))
- u_cmsdk_uart_capture(
+ nanosoc_uart_capture #(.LOGFILENAME("uart2.log"))
+ u_nanosoc_uart_capture(
.RESETn (NRST),
.CLK (uart_clk), //PCLK),
.RXD (UARTXD), // UART 2 use for StdOut
@@ -266,9 +266,9 @@ wire rxd8_ready;
wire rxd8_valid;
wire [7:0] rxd8_data ;
-axi_stream_io_8_txd_from_file
+nanosoc_axi_stream_io_8_txd_from_file
#(.TXDFILENAME(ADP_FILENAME))
- u_axi_stream_io_8_txd_from_file
+ u_nanosoc_axi_stream_io_8_txd_from_file
(
.aclk (XTAL1),
.aresetn (NRST),
@@ -297,8 +297,8 @@ wire ft_miosio_z;
wire ft_miosio_i = P1[2]; // & ft_miosio_z;
assign P1[2] = (ft_miosio_z) ? 1'bz : ft_miosio_o;
-ft1248x1_to_axi_streamio_v1_0
- u_ft1248x1_to_axi_streamio_v1_0
+nanosoc_ft1248x1_to_axi_streamio_v1_0
+ u_nanosoc_ft1248x1_to_axi_streamio_v1_0
(
.ft_clk_i (ft_clk_out),
.ft_ssn_i (ft_ssn_out),
@@ -316,9 +316,9 @@ ft1248x1_to_axi_streamio_v1_0
.txd_tdata8_o (rxd8_data)
);
-axi_stream_io_8_rxd_to_file
+nanosoc_axi_stream_io_8_rxd_to_file
#(.RXDFILENAME("ft1248_out.log"))
- u_axi_stream_io_8_rxd_to_file
+ u_nanosoc_axi_stream_io_8_rxd_to_file
(
.aclk (XTAL1),
.aresetn (NRST),
@@ -327,8 +327,8 @@ axi_stream_io_8_rxd_to_file
.rxd8_data (rxd8_data)
);
-track_tb_iostream
- u_track_tb_iostream
+nanosoc_track_tb_iostream
+ u_nanosoc_track_tb_iostream
(
.aclk (XTAL1),
.aresetn (NRST),
@@ -344,8 +344,8 @@ wire ft_clk2uart;
wire ft_rxd2uart;
wire ft_txd2uart;
-ft1248x1_track
- u_ft1248x1_track
+nanosoc_ft1248x1_track
+ u_nanosoc_ft1248x1_track
(
.ft_clk_i (ft_clk_out),
.ft_ssn_i (ft_ssn_out),
@@ -559,8 +559,8 @@ ft1248x1_track
`define DMAC_TRACK_PATH u_track_pl230_udma
- dma_log_to_file #(.FILENAME("dma230.log"),.NUM_CHNLS(2),.NUM_CHNL_BITS(1),.TIMESTAMP(1))
- u_dma_log_to_file (
+ nanosoc_dma_log_to_file #(.FILENAME("dma230.log"),.NUM_CHNLS(2),.NUM_CHNL_BITS(1),.TIMESTAMP(1))
+ u_nanosoc_dma_log_to_file (
.hclk (`DMAC_TRACK_PATH.hclk),
.hresetn (`DMAC_TRACK_PATH.hresetn),
// AHB-Lite Master Interface
@@ -701,26 +701,26 @@ ft1248x1_track
initial begin
`ifdef CORTEX_M0DESIGNSTART
`ifdef CORTEX_M0
- $display("ERROR (tb_cmsdk_mcu.v) in CPU preprocessing directive : Both CORTEX_M0DESIGNSTART and CORTEX_M0 are set. Please use only one.");
+ $display("ERROR (nanosoc_tb.v) in CPU preprocessing directive : Both CORTEX_M0DESIGNSTART and CORTEX_M0 are set. Please use only one.");
$stop;
`endif
`endif
`ifdef CORTEX_M0DESIGNSTART
`ifdef CORTEX_M0PLUS
- $display("ERROR (tb_cmsdk_mcu.v) in CPU preprocessing directive : Both CORTEX_M0DESIGNSTART and CORTEX_M0PLUS are set. Please use only one.");
+ $display("ERROR (nanosoc_tb.v) in CPU preprocessing directive : Both CORTEX_M0DESIGNSTART and CORTEX_M0PLUS are set. Please use only one.");
$stop;
`endif
`endif
`ifdef CORTEX_M0
`ifdef CORTEX_M0PLUS
- $display("ERROR (tb_cmsdk_mcu.v) in CPU preprocessing directive : Both CORTEX_M0 and CORTEX_M0PLUS are set. Please use only one.");
+ $display("ERROR (nanosoc_tb.v) in CPU preprocessing directive : Both CORTEX_M0 and CORTEX_M0PLUS are set. Please use only one.");
$stop;
`endif
`endif
`ifdef CORTEX_M0DESIGNSTART
`ifdef CORTEX_M0
`ifdef CORTEX_M0PLUS
- $display("ERROR (tb_cmsdk_mcu.v) in CPU preprocessing directive : All of CORTEX_M0DESIGNSTART, CORTEX_M0 and CORTEX_M0PLUS are set. Please use only one.");
+ $display("ERROR (nanosoc_tb.v) in CPU preprocessing directive : All of CORTEX_M0DESIGNSTART, CORTEX_M0 and CORTEX_M0PLUS are set. Please use only one.");
$stop;
`endif
`endif
@@ -731,7 +731,7 @@ ft1248x1_track
`else
`ifdef CORTEX_M0DESIGNSTART
`else
- $display("ERROR (tb_cmsdk_mcu.v) in CPU preprocessing directive : None of CORTEX_M0DESIGNSTART, CORTEX_M0 and CORTEX_M0PLUS are set. Please select one.");
+ $display("ERROR (nanosoc_tb.v) in CPU preprocessing directive : None of CORTEX_M0DESIGNSTART, CORTEX_M0 and CORTEX_M0PLUS are set. Please select one.");
$stop;
`endif
`endif
--
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