Changed soclabs paths for new nanosoc paths in build_mcu_fpga_ip.tcl

system/fpga_imp/scripts/build_mcu_fpga_ip.tcl

@@ -57,34 +57,34 @@ source scripts/rtl_source_soclabs_ip.tcl
 #source scripts/rtl_source_fpga_ip.tcl
 
 # soclabs modified mcu system 
-set soc_vlog ../verilog
-read_verilog  $soc_vlog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix_default_slave.v
-read_verilog  $soc_vlog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix_lite.v
-read_verilog  $soc_vlog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix.v
-read_verilog  $soc_vlog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_Arbiter.v
-read_verilog  $soc_vlog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MasterInput.v
-read_verilog  $soc_vlog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_adp.v
-read_verilog  $soc_vlog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_cpu.v
-read_verilog  $soc_vlog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_dma2.v
-read_verilog  $soc_vlog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_dma.v
-read_verilog  $soc_vlog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_SlaveOutput.v
-read_verilog  $soc_vlog/ahb_bootrom.v
-read_verilog  $soc_vlog/bootrom.v
-read_verilog  $soc_vlog/cmsdk_ahb_cs_rom_table.v
-read_verilog  $soc_vlog/cmsdk_apb_usrt.v
+set soc_vlog ../src
+read_verilog  $soc_vlog/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_busmatrix_default_slave.v
+read_verilog  $soc_vlog/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_busmatrix_lite.v
+read_verilog  $soc_vlog/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_busmatrix.v
+read_verilog  $soc_vlog/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_arbiter.v 
+read_verilog  $soc_vlog/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_inititator_input.v 
+read_verilog  $soc_vlog/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_matrix_decode_adp.v
+read_verilog  $soc_vlog/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_matrix_decode_cpu.v
+read_verilog  $soc_vlog/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_matrix_decode_dma2.v
+read_verilog  $soc_vlog/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_matrix_decode_dma.v
+read_verilog  $soc_vlog/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_target_output.v
+read_verilog  $soc_vlog/verilog/nanosoc_ahb_bootrom.v
+read_verilog  $soc_vlog/verilog/bootrom.v
+read_verilog  $soc_vlog/verilog/nanosoc_ahb_cs_rom_table.v
+read_verilog  $soc_vlog/verilog/nanosoc_apb_usrt.v
 ##read_verilog  $soc_vlog/cmsdk_clkreset.v
-read_verilog  $soc_vlog/cmsdk_ft1248x1_adpio.v
-read_verilog  $soc_vlog/cmsdk_mcu_clkctrl.v
-read_verilog  $soc_vlog/cmsdk_mcu_pin_mux.v
-read_verilog  $soc_vlog/cmsdk_mcu_stclkctrl.v
-read_verilog  $soc_vlog/cmsdk_mcu_sysctrl.v
+read_verilog  ../test_io/verilog/nanosoc_ft1248x1_adpio.v  
+read_verilog  $soc_vlog/verilog/nanosoc_mcu_clkctrl.v
+read_verilog  $soc_vlog/verilog/nanosoc_mcu_pin_mux.v
+read_verilog  $soc_vlog/verilog/nanosoc_mcu_stclkctrl.v
+read_verilog  $soc_vlog/verilog/nanosoc_mcu_sysctrl.v
 ##read_verilog  $soc_vlog/cmsdk_uart_capture.v
-read_verilog  $soc_vlog/nanosoc_cpu.v
-read_verilog  $soc_vlog/nanosoc_sys_ahb_decode.v
-read_verilog  $soc_vlog/nanosoc_sysio.v
-read_verilog  $soc_vlog/soclabs_ahb_aes128_ctrl.v
-read_verilog  $soc_vlog/nanosoc_chip.v
-read_verilog  $soc_vlog/nanosoc_chip_pads.v
+read_verilog  $soc_vlog/verilog/nanosoc_cpu.v
+read_verilog  $soc_vlog/verilog/nanosoc_sys_ahb_decode.v
+read_verilog  $soc_vlog/verilog/nanosoc_sysio.v
+read_verilog  ../aes/src/soclabs_ahb_aes128_ctrl.v 
+read_verilog  $soc_vlog/verilog/nanosoc_chip.v
+read_verilog  $soc_vlog/verilog/nanosoc_chip_pads.v
 
 set_property top nanosoc_chip [current_fileset]