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Commit 6bb5c478 authored by dam1n19's avatar dam1n19
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SOC1-167: Attempt 3? at verilog_define

parent 91bcc715
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...@@ -57,7 +57,6 @@ source scripts/rtl_source_soclabs_ip.tcl ...@@ -57,7 +57,6 @@ source scripts/rtl_source_soclabs_ip.tcl
#source scripts/rtl_source_fpga_ip.tcl #source scripts/rtl_source_fpga_ip.tcl
# soclabs modified mcu system # soclabs modified mcu system
set_property verilog_define {NANOSOC_EXPANSION_REGION=1} [current_fileset]
set soc_vlog ../src set soc_vlog ../src
read_verilog $soc_vlog/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_busmatrix_default_slave.v read_verilog $soc_vlog/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_busmatrix_default_slave.v
...@@ -89,6 +88,7 @@ read_verilog ../aes/src/soclabs_ahb_aes128_ctrl.v ...@@ -89,6 +88,7 @@ read_verilog ../aes/src/soclabs_ahb_aes128_ctrl.v
read_verilog $soc_vlog/verilog/nanosoc_chip.v read_verilog $soc_vlog/verilog/nanosoc_chip.v
read_verilog $soc_vlog/verilog/nanosoc_chip_pads.v read_verilog $soc_vlog/verilog/nanosoc_chip_pads.v
set_property verilog_define {NANOSOC_EXPANSION_REGION=1} [current_fileset]
set_property top nanosoc_chip [current_fileset] set_property top nanosoc_chip [current_fileset]
# FPGA specific timing constraints # FPGA specific timing constraints
......
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