From 6bb5c47836730408be1ca81c10c62eeafa85e3a9 Mon Sep 17 00:00:00 2001
From: dam1n19 <dam1n19@soton.ac.uk>
Date: Tue, 2 May 2023 12:25:19 +0100
Subject: [PATCH] SOC1-167: Attempt 3? at verilog_define
---
system/fpga_imp/scripts/build_mcu_fpga_ip.tcl | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/system/fpga_imp/scripts/build_mcu_fpga_ip.tcl b/system/fpga_imp/scripts/build_mcu_fpga_ip.tcl
index 595e676..cd2d585 100644
--- a/system/fpga_imp/scripts/build_mcu_fpga_ip.tcl
+++ b/system/fpga_imp/scripts/build_mcu_fpga_ip.tcl
@@ -57,7 +57,6 @@ source scripts/rtl_source_soclabs_ip.tcl
#source scripts/rtl_source_fpga_ip.tcl
# soclabs modified mcu system
-set_property verilog_define {NANOSOC_EXPANSION_REGION=1} [current_fileset]
set soc_vlog ../src
read_verilog $soc_vlog/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_busmatrix_default_slave.v
@@ -89,6 +88,7 @@ read_verilog ../aes/src/soclabs_ahb_aes128_ctrl.v
read_verilog $soc_vlog/verilog/nanosoc_chip.v
read_verilog $soc_vlog/verilog/nanosoc_chip_pads.v
+set_property verilog_define {NANOSOC_EXPANSION_REGION=1} [current_fileset]
set_property top nanosoc_chip [current_fileset]
# FPGA specific timing constraints
--
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