diff --git a/system/fpga_imp/scripts/build_mcu_fpga_ip.tcl b/system/fpga_imp/scripts/build_mcu_fpga_ip.tcl
index 595e676941119418a3b6e323e4b021e24451c7af..cd2d58554c57be892c343623b6ccd290eea7428d 100644
--- a/system/fpga_imp/scripts/build_mcu_fpga_ip.tcl
+++ b/system/fpga_imp/scripts/build_mcu_fpga_ip.tcl
@@ -57,7 +57,6 @@ source scripts/rtl_source_soclabs_ip.tcl
 #source scripts/rtl_source_fpga_ip.tcl
 
 # soclabs modified mcu system 
-set_property verilog_define {NANOSOC_EXPANSION_REGION=1} [current_fileset]
 
 set soc_vlog ../src
 read_verilog  $soc_vlog/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_busmatrix_default_slave.v
@@ -89,6 +88,7 @@ read_verilog  ../aes/src/soclabs_ahb_aes128_ctrl.v
 read_verilog  $soc_vlog/verilog/nanosoc_chip.v
 read_verilog  $soc_vlog/verilog/nanosoc_chip_pads.v
 
+set_property verilog_define {NANOSOC_EXPANSION_REGION=1} [current_fileset]
 set_property top nanosoc_chip [current_fileset]
 
 # FPGA specific timing constraints