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ASIC/44pin/Cadence/scripts/design_import.tcl
View file @ f783f487
......@@ -14,10 +14,11 @@ read_mmmc nanosoc.mmmc
# Set library paths
# !! EDIT THIS TO YOUR PATHS IN YOUR ENVIRONMENT
set TECH_LEF $::env(PHYS_IP)/arm/tsmc/cln65lp/arm_tech/r2p0/lef/1p9m_6x2z/sc12_tech.lef
set TECH_LEF /home/dwn1c21/SoC-Labs/util/PRTF_EDI_65nm_001_Cad_V24a/PRTF_EDI_N65_9M_6X1Z1U_RDL.24a.tlef
#$::env(PHYS_IP)/arm/tsmc/cln65lp/arm_tech/r2p0/lef/1p9m_6x2z/sc12_tech.lef
set BASE_LEF $::env(PHYS_IP)/arm/tsmc/cln65lp/sc12_base_rvt/r0p0/lef/sc12_cln65lp_base_rvt.lef
set IO_PAD_LEF /home/dwn1c21/SoC-Labs/phys_ip/tsmc/cln65lp/Backend/lef/tpbn65v_9lm.lef
set IO_PAD_DRIVER_LEF /home/dwn1c21/SoC-Labs/phys_ip/tsmc/cln65lp/Backend/lef/tpdn65lpnv2od3_9lm.lef
set IO_PAD_LEF /home/dwn1c21/SoC-Labs/phys_ip/TSMC/65/iolib/tpbn65v_200b_FE/TSMCHOME/digital/Back_End/lef/tpbn65v_200b/cup/9m/9M_6X1Z1U/lef/tpbn65v_9lm.lef
set IO_PAD_DRIVER_LEF /home/dwn1c21/SoC-Labs/phys_ip/TSMC/65/CMOS/LP/IO2.5V/iolib/linear/tpdn65lpnv2od3_200a_FE/TSMCHOME/digital/Back_End/lef/tpdn65lpnv2od3_140b/mt_2/9lm/lef/tpdn65lpnv2od3_9lm.lef
# !! THESE SHOULD BE CORRECT FOR ANY ENVIRONMENT AS THEY ARE GENERATED BY MAKEFILE
......
ASIC/44pin/Cadence/scripts/design_import_noDFT.tcl
View file @ f783f487
......@@ -14,10 +14,11 @@ read_mmmc nanosoc.mmmc
# Set library paths
# !! EDIT THIS TO YOUR PATHS IN YOUR ENVIRONMENT
set TECH_LEF $::env(PHYS_IP)/arm/tsmc/cln65lp/arm_tech/r2p0/lef/1p9m_6x2z/sc12_tech.lef
set TECH_LEF /home/dwn1c21/SoC-Labs/util/PRTF_EDI_65nm_001_Cad_V24a/PRTF_EDI_N65_9M_6X1Z1U_RDL.24a.tlef
#$::env(PHYS_IP)/arm/tsmc/cln65lp/arm_tech/r2p0/lef/1p9m_6x2z/sc12_tech.lef
set BASE_LEF $::env(PHYS_IP)/arm/tsmc/cln65lp/sc12_base_rvt/r0p0/lef/sc12_cln65lp_base_rvt.lef
set IO_PAD_LEF /home/dwn1c21/SoC-Labs/phys_ip/tsmc/cln65lp/Backend/lef/tpbn65v_9lm.lef
set IO_PAD_DRIVER_LEF /home/dwn1c21/SoC-Labs/phys_ip/tsmc/cln65lp/Backend/lef/tpdn65lpnv2od3_9lm.lef
set IO_PAD_LEF /home/dwn1c21/SoC-Labs/phys_ip/TSMC/65/iolib/tpbn65v_200b_FE/TSMCHOME/digital/Back_End/lef/tpbn65v_200b/cup/9m/9M_6X1Z1U/lef/tpbn65v_9lm.lef
set IO_PAD_DRIVER_LEF /home/dwn1c21/SoC-Labs/phys_ip/TSMC/65/CMOS/LP/IO2.5V/iolib/linear/tpdn65lpnv2od3_200a_FE/TSMCHOME/digital/Back_End/lef/tpdn65lpnv2od3_140b/mt_2/9lm/lef/tpdn65lpnv2od3_9lm.lef
# !! THESE SHOULD BE CORRECT FOR ANY ENVIRONMENT AS THEY ARE GENERATED BY MAKEFILE
......
ASIC/44pin/Cadence/scripts/filler.tcl 0 → 100644
View file @ f783f487
add_fillers -base_cells [list FILL128_A12TR WELLANTENNATIEPW2_A12TR FILLTIE8_A12TR FILLTIE64_A12TR FILLTIE4_A12TR FILLTIE32_A12TR FILLTIE2_A12TR FILLTIE16_A12TR FILLTIE128_A12TR FILLCAPTIE8_A12TR] -prefix FILLER -fill_gap -merge true -power_domain ACCEL -check_drc true
add_fillers -base_cells [list FILL128_A12TR WELLANTENNATIEPW2_A12TR FILLTIE8_A12TR FILLTIE64_A12TR FILLTIE4_A12TR FILLTIE32_A12TR FILLTIE2_A12TR FILLTIE16_A12TR FILLTIE128_A12TR FILLCAPTIE8_A12TR] -prefix FILLER -fill_gap -merge true -power_domain TOP -check_drc true
add_filler_gaps 0.8 -effort high
check_filler > check_filler.log
add_fillers -base_cells [list FILL128_A12TR WELLANTENNATIEPW2_A12TR FILLTIE8_A12TR FILLTIE64_A12TR FILLTIE4_A12TR FILLTIE32_A12TR FILLTIE2_A12TR FILLTIE16_A12TR FILLTIE128_A12TR FILLCAPTIE8_A12TR] -prefix FILLER -power_domain ACCEL -check_drc true -fix_drc
add_fillers -base_cells [list FILL128_A12TR WELLANTENNATIEPW2_A12TR FILLTIE8_A12TR FILLTIE64_A12TR FILLTIE4_A12TR FILLTIE32_A12TR FILLTIE2_A12TR FILLTIE16_A12TR FILLTIE128_A12TR FILLCAPTIE8_A12TR] -prefix FILLER -power_domain TOP -check_drc true -fix_drc
ASIC/44pin/Cadence/scripts/genus.tcl
View file @ f783f487
......@@ -11,7 +11,7 @@
#
# Copyright (C) 2023, SoC Labs (www.soclabs.org)
#-----------------------------------------------------------------------------
set_multi_cpu_usage -local_cpu 8
## -- Setup libraries -- ##
set_db init_lib_search_path "/home/dwn1c21/SoC-Labs/phys_ip/tsmc/cln65lp/Front_End/timing_power_noise/NLDM/tpdn65lpnv2od3_200a/ $::env(PHYS_IP)/arm/tsmc/cln65lp/sc12_base_rvt/r0p0/lib/ $::env(SOCLABS_PROJECT_DIR)/memories/rf_16k/ $::env(SOCLABS_PROJECT_DIR)/memories/rf_08k/ $::env(SOCLABS_PROJECT_DIR)/memories/bootrom/"
set BASE_LIB sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c.lib
......@@ -54,7 +54,7 @@ set_db hinst:nanosoc_chip_pads/u_nanosoc_chip_cfg .dft_dont_scan true
define_test_signal -name TEST -active high -shared_input -hookup_pin u_nanosoc_chip/test_i -function test_mode -index 0 TEST
define_test_signal -name CLK -active high -hookup_pin u_nanosoc_chip/clk_i -function test_clock -index 0 CLK
define_test_signal -name NRST -active low -hookup_pin u_nanosoc_chip/nrst_i -function async_set_reset -index 0 NRST
define_test_signal -name SWDCK -active high -shared_input -hookup_pin u_nanosoc_chip_cfg/soc_scan_enable -function shift_enable -default -index 0 SWDCK
define_test_signal -name SE -active high -shared_input -hookup_pin u_nanosoc_chip_cfg/soc_scan_enable -function shift_enable -default -index 0 SE
define_scan_chain -name chain_ACCEL -sdi P0[0] -hookup_pin_sdi u_nanosoc_chip_cfg/soc_scan_in[0] -sdo P1[0] -hookup_pin_sdo u_nanosoc_chip_cfg/soc_scan_out[0] -shared_output -shared_input
define_scan_chain -name chain_TOP_1 -sdi P0[1] -hookup_pin_sdi u_nanosoc_chip_cfg/soc_scan_in[1] -sdo P1[1] -hookup_pin_sdo u_nanosoc_chip_cfg/soc_scan_out[1] -shared_output -shared_input
define_scan_chain -name chain_TOP_2 -sdi P0[2] -hookup_pin_sdi u_nanosoc_chip_cfg/soc_scan_in[2] -sdo P1[2] -hookup_pin_sdo u_nanosoc_chip_cfg/soc_scan_out[2] -shared_output -shared_input
......
ASIC/44pin/Cadence/scripts/genus_nodft.tcl
View file @ f783f487
......@@ -11,7 +11,7 @@
#
# Copyright (C) 2023, SoC Labs (www.soclabs.org)
#-----------------------------------------------------------------------------
set_multi_cpu_usage -local_cpu 8
## -- Setup libraries -- ##
set_db init_lib_search_path "/home/dwn1c21/SoC-Labs/phys_ip/tsmc/cln65lp/Front_End/timing_power_noise/NLDM/tpdn65lpnv2od3_200a/ $::env(PHYS_IP)/arm/tsmc/cln65lp/sc12_base_rvt/r0p0/lib/ $::env(SOCLABS_PROJECT_DIR)/memories/rf_16k/ $::env(SOCLABS_PROJECT_DIR)/memories/rf_08k/ $::env(SOCLABS_PROJECT_DIR)/memories/bootrom/"
set BASE_LIB sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c.lib
......@@ -50,6 +50,7 @@ read_sdc $::env(SOCLABS_NANOSOC_TECH_DIR)/ASIC/constraints.sdc
set_db syn_generic_effort high
set_db syn_map_effort high
set_db syn_opt_effort high
syn_generic
syn_map
......
ASIC/44pin/Cadence/scripts/io_plan.tcl
View file @ f783f487
......@@ -21,10 +21,10 @@ delete_io_fillers -cell PFILLER0005
read_io_file nanosoc_io_plan.io
add_io_fillers -cells PCORNER -prefix CORNER -side n -from -300 -to 300
add_io_fillers -cells PCORNER -prefix CORNER -side e -from 1380 -to 3000
add_io_fillers -cells PCORNER -prefix CORNER -side s -from 880 -to 2000
add_io_fillers -cells PCORNER -prefix CORNER -side w -from -300 -to 300
add_io_fillers -cells PCORNER -prefix CORNER -side n -from 880 -to 1000
add_io_fillers -cells PCORNER -prefix CORNER -side e -from 0 -to 120
add_io_fillers -cells PCORNER -prefix CORNER -side s -from 0 -to 120
add_io_fillers -cells PCORNER -prefix CORNER -side w -from 1380 -to 1500
add_io_fillers -cells PFILLER20 -prefix FILLER -side n
add_io_fillers -cells PFILLER20 -prefix FILLER -side e
......
ASIC/44pin/Cadence/scripts/nanosoc.mmmc
View file @ f783f487
......@@ -5,7 +5,7 @@ set tech_path ${phys_lib}/arm/tsmc/cln65lp/arm_tech/r2p0
set ram_path /home/dwn1c21/SoC-Labs/TAPEOUT_feb2024/Fanis/fast-knn-accelerator-project/memories/rf_16k/
set ram_08k_path /home/dwn1c21/SoC-Labs/TAPEOUT_feb2024/Fanis/fast-knn-accelerator-project/memories/rf_08k/
set rom_path /home/dwn1c21/SoC-Labs/TAPEOUT_feb2024/Fanis/fast-knn-accelerator-project/memories/bootrom/
set IO_driver_path /home/dwn1c21/SoC-Labs/phys_ip/tsmc/cln65lp/Front_End/timing_power_noise/NLDM/tpdn65lpnv2od3_200a/
set IO_driver_path /home/dwn1c21/SoC-Labs/phys_ip/TSMC/65/CMOS/LP/IO2.5V/iolib/linear/tpdn65lpnv2od3_200a_FE/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tpdn65lpnv2od3_200a/
create_library_set -name default_libset_max\
-timing\
......@@ -19,10 +19,18 @@ create_library_set -name default_libset_min\
-si\
[list ${base_path}/celtic/sc12_cln65lp_base_rvt_ff_typical_min_1p32v_m40c.cdB]
create_library_set -name typical_libset\
-timing\
[list ${base_path}/lib/sc12_cln65lp_base_rvt_tt_typical_max_1p20v_25c.lib ${ram_path}/rf_16k_tt_1p20v_1p20v_25c.lib ${ram_08k_path}/rf_08k_tt_1p20v_1p20v_25c.lib ${rom_path}/rom_via_tt_1p20v_1p20v_25c.lib ${IO_driver_path}/tpdn65lpnv2od3tc.lib] \
-si\
[list ${base_path}/celtic/sc12_cln65lp_base_rvt_tt_typical_max_1p20v_25c.cdB]
create_timing_condition -name default_mapping_tc_2\
-library_sets [list default_libset_min]
create_timing_condition -name default_mapping_tc_1\
-library_sets [list default_libset_max]
create_timing_condition -name typical_mapping\
-library_sets [list typical_libset]
create_rc_corner -name default_rc_corner_worst\
-pre_route_res 1\
......@@ -69,6 +77,10 @@ create_delay_corner -name default_delay_corner_min\
-timing_condition default_mapping_tc_2\
-rc_corner default_rc_corner_best
create_delay_corner -name typical_delay_corner\
-timing_condition typical_mapping\
-rc_corner default_rc_corner_typical
create_constraint_mode -name default_constraint_mode\
-sdc_files\
[list ../../../constraints.sdc]
......@@ -81,5 +93,6 @@ create_analysis_view -name default_analysis_view_hold -constraint_mode default_c
create_analysis_view -name typical_analysis_view_setup -constraint_mode default_constraint_mode -delay_corner default_delay_corner_ocv
create_analysis_view -name typical_analysis_view_hold -constraint_mode default_constraint_mode -delay_corner default_delay_corner_ocv
create_analysis_view -name typical_analysis_view -constraint_mode default_constraint_mode -delay_corner typical_delay_corner
set_analysis_view -setup [list default_analysis_view_setup] -hold [list default_analysis_view_hold]
set_analysis_view -setup [list default_analysis_view_setup typical_analysis_view] -hold [list default_analysis_view_hold typical_analysis_view]
ASIC/44pin/Cadence/scripts/nanosoc_io_plan.io
View file @ f783f487
......@@ -37,7 +37,7 @@
(bottom
(inst name="uPAD_P0_02" offset=149.29 place_status=placed )
(inst name="uPAD_VDDACC_1" offset=257.86 place_status=placed )
(inst name="uPAD_VDDIO_1" offset=366.43 place_status=placed )
(inst name="uPAD_SE_I" offset=366.43 place_status=placed )
(inst name="uPAD_VDD_1" offset=475.00 place_status=placed )
(inst name="uPAD_VSS_1" offset=583.57 place_status=placed )
(inst name="uPAD_P0_01" offset=692.14 place_status=placed )
......
ASIC/44pin/Cadence/scripts/place.tcl
View file @ f783f487
......@@ -9,9 +9,9 @@ set_db design_process_node 65
set_db place_global_cong_effort auto
set_db place_global_timing_effort high
### Uniform Cell Distribution
### Uniform Cell Distribution and fill gap
set_db place_global_uniform_density true
set_db place_detail_legalization_inst_gap 2
### Placement Mode Config
set_db place_design_floorplan_mode false
......@@ -19,3 +19,6 @@ place_design
### Delay Calculation
write_sdf design.sdf -ideal_clock_network
set_db add_tieoffs_max_fanout 10
add_tieoffs -lib_cell {TIELO_X1M_A12TR TIEHI_X1M_A12TR} -prefix LTIE -power_domain TOP -exclude_pin tieoff_exclude
add_tieoffs -lib_cell {TIELO_X1M_A12TR TIEHI_X1M_A12TR} -prefix LTIE -power_domain ACCEL -exclude_pin tieoff_exclude
ASIC/44pin/Cadence/scripts/place_bondpads.tcl 0 → 100644
View file @ f783f487
eval_legacy {addInst -cell PAD60LU -inst BPAD_TEST_I -loc {149.29 1428} -ori R180}
eval_legacy {addInst -cell PAD60LU -inst BPAD_SWDCK_I -loc {257.86 1428} -ori R180}
eval_legacy {addInst -cell PAD60LU -inst BPAD_VDD_3 -loc {366.43 1428} -ori R180}
eval_legacy {addInst -cell PAD60LU -inst BPAD_VSS_3 -loc {475.00 1428} -ori R180}
eval_legacy {addInst -cell PAD60LU -inst BPAD_VDDIO_3 -loc {583.57 1428} -ori R180}
eval_legacy {addInst -cell PAD60LU -inst BPAD_P1_00 -loc {692.14 1428} -ori R180}
eval_legacy {addInst -cell PAD60LU -inst BPAD_P1_01 -loc {800.71 1428} -ori R180}
eval_legacy {addInst -cell PAD60LU -inst BPAD_P0_04 -loc {0.0 146.25} -ori R270}
eval_legacy {addInst -cell PAD60LU -inst BPAD_P0_05 -loc {0.0 251.25} -ori R270}
eval_legacy {addInst -cell PAD60LU -inst BPAD_P0_03 -loc {0.0 356.25} -ori R270}
eval_legacy {addInst -cell PAD60LU -inst BPAD_VDDACC_0 -loc {0.0 461.25} -ori R270}
eval_legacy {addInst -cell PAD60LU -inst BPAD_VSS_0 -loc {0.0 566.25} -ori R270}
eval_legacy {addInst -cell PAD60LU -inst BPAD_CLK_I -loc {0.0 671.25} -ori R270}
eval_legacy {addInst -cell PAD60LU -inst BPAD_VDD_0 -loc {0.0 776.25} -ori R270}
eval_legacy {addInst -cell PAD60LU -inst BPAD_VDDIO_0 -loc {0.0 881.25} -ori R270}
eval_legacy {addInst -cell PAD60LU -inst BPAD_SWDIO_IO -loc {0.0 986.25} -ori R270}
eval_legacy {addInst -cell PAD60LU -inst BPAD_VSSIO_0 -loc {0.0 1091.25} -ori R270}
eval_legacy {addInst -cell PAD60LU -inst BPAD_P0_06 -loc {0.0 1196.25} -ori R270}
eval_legacy {addInst -cell PAD60LU -inst BPAD_P0_07 -loc {0.0 1301.25} -ori R270}
eval_legacy {addInst -cell PAD60LU -inst BPAD_P0_02 -loc {149.29 0} -ori R0}
eval_legacy {addInst -cell PAD60LU -inst BPAD_VDDACC_1 -loc {257.86 0} -ori R0}
eval_legacy {addInst -cell PAD60LU -inst BPAD_VDDIO_1 -loc {366.43 0} -ori R0}
eval_legacy {addInst -cell PAD60LU -inst BPAD_VDD_1 -loc {475.00 0} -ori R0}
eval_legacy {addInst -cell PAD60LU -inst BPAD_VSS_1 -loc {583.57 0} -ori R0}
eval_legacy {addInst -cell PAD60LU -inst BPAD_P0_01 -loc {692.14 0} -ori R0}
eval_legacy {addInst -cell PAD60LU -inst BPAD_P0_00 -loc {800.71 0} -ori R0}
eval_legacy {addInst -cell PAD60LU -inst BPAD_P1_07 -loc {928 146.25} -ori R90}
eval_legacy {addInst -cell PAD60LU -inst BPAD_P1_06 -loc {928 251.25} -ori R90}
eval_legacy {addInst -cell PAD60LU -inst BPAD_VSSIO_1 -loc {928 356.25} -ori R90}
eval_legacy {addInst -cell PAD60LU -inst BPAD_P1_03 -loc {928 461.25} -ori R90}
eval_legacy {addInst -cell PAD60LU -inst BPAD_P1_02 -loc {928 566.25} -ori R90}
eval_legacy {addInst -cell PAD60LU -inst BPAD_VDDACC_2 -loc {928 671.25} -ori R90}
eval_legacy {addInst -cell PAD60LU -inst BPAD_VDD_2 -loc {928 776.25} -ori R90}
eval_legacy {addInst -cell PAD60LU -inst BPAD_VSS_2 -loc {928 881.25} -ori R90}
eval_legacy {addInst -cell PAD60LU -inst BPAD_VDDIO_2 -loc {928 986.25} -ori R90}
eval_legacy {addInst -cell PAD60LU -inst BPAD_NRST_I -loc {928 1091.25} -ori R90}
eval_legacy {addInst -cell PAD60LU -inst BPAD_P1_04 -loc {928 1196.25} -ori R90}
eval_legacy {addInst -cell PAD60LU -inst BPAD_P1_05 -loc {928 1301.25} -ori R90}
ASIC/44pin/Cadence/scripts/place_macros.tcl
View file @ f783f487
......@@ -11,12 +11,14 @@
# relative floorplan
gui_set_draw_view fplan
delete_relative_floorplan -all
create_relative_floorplan -ref_type core_boundary -horizontal_edge_separate {1 -4.8 1} -vertical_edge_separate {2 -2.4 2} -place u_nanosoc_chip_u_system/u_ss_expansion_u_region_expram_l_u_expram_l_u_sram_genblk1.u_rf_sp_hdf
create_relative_floorplan -ref_type object -horizontal_edge_separate {3 -12 1} -vertical_edge_separate {3 0 3} -place u_nanosoc_chip_u_system/u_ss_expansion_u_region_expram_h_u_expram_h_u_sram_genblk1.u_rf_sp_hdf -ref u_nanosoc_chip_u_system/u_ss_expansion_u_region_expram_l_u_expram_l_u_sram_genblk1.u_rf_sp_hdf
create_relative_floorplan -ref_type object -horizontal_edge_separate {3 -12 1} -vertical_edge_separate {3 0 3} -place u_nanosoc_chip_u_system/u_ss_cpu_u_region_imem_0_u_imem_0_u_sram_genblk1.u_rf_sp_hdf -ref u_nanosoc_chip_u_system/u_ss_expansion_u_region_expram_h_u_expram_h_u_sram_genblk1.u_rf_sp_hdf
create_relative_floorplan -ref_type object -orient R0 -horizontal_edge_separate {3 -12 1} -vertical_edge_separate {3 0 3} -place u_nanosoc_chip_u_system/u_ss_cpu_u_region_dmem_0_u_dmem_0_u_sram_genblk1.u_rf_sp_hdf -ref u_nanosoc_chip_u_system/u_ss_cpu_u_region_imem_0_u_imem_0_u_sram_genblk1.u_rf_sp_hdf
create_relative_floorplan -ref_type core_boundary -horizontal_edge_separate {1 -4.8 1} -vertical_edge_separate {2 -2.4 2} -place u_nanosoc_chip_u_system/u_ss_cpu_u_region_dmem_0_u_dmem_0_u_sram_genblk1.u_rf_sp_hdf
create_relative_floorplan -ref_type object -horizontal_edge_separate {3 -12 1} -vertical_edge_separate {3 0 3} -place u_nanosoc_chip_u_system/u_ss_cpu_u_region_imem_0_u_imem_0_u_sram_genblk1.u_rf_sp_hdf -ref u_nanosoc_chip_u_system/u_ss_cpu_u_region_dmem_0_u_dmem_0_u_sram_genblk1.u_rf_sp_hdf
create_relative_floorplan -ref_type object -horizontal_edge_separate {3 -12 1} -vertical_edge_separate {3 0 3} -place u_nanosoc_chip_u_system/u_ss_expansion_u_region_expram_l_u_expram_l_u_sram_genblk1.u_rf_sp_hdf -ref u_nanosoc_chip_u_system/u_ss_cpu_u_region_imem_0_u_imem_0_u_sram_genblk1.u_rf_sp_hdf
create_relative_floorplan -ref_type object -orient R0 -horizontal_edge_separate {3 -12 1} -vertical_edge_separate {3 0 3} -place u_nanosoc_chip_u_system/u_ss_expansion_u_region_expram_h_u_expram_h_u_sram_genblk1.u_rf_sp_hdf -ref u_nanosoc_chip_u_system/u_ss_expansion_u_region_expram_l_u_expram_l_u_sram_genblk1.u_rf_sp_hdf
create_relative_floorplan -ref_type core_boundary -orient R0 -horizontal_edge_separate {1 -4.8 1} -vertical_edge_separate {0 2.4 0} -place u_nanosoc_chip_u_system/u_ss_cpu_u_region_bootrom_0_u_bootrom_cpu_0_u_bootrom_u_sl_rom
move_obj u_nanosoc_chip_u_system/u_ss_expansion_u_region_exp_u_ss_accelerator -point {500 500}
update_floorplan_obj -obj u_nanosoc_chip_u_system/u_ss_expansion_u_region_exp_u_ss_accelerator -rects {137.6 137.6 862.4 420}
add_fences -hinst u_nanosoc_chip_u_system/u_ss_expansion_u_region_exp_u_ss_accelerator -min_gap 2.4
......
ASIC/44pin/Cadence/scripts/pnr_flow.tcl
View file @ f783f487
......@@ -14,9 +14,10 @@
set SC_GDS2 $::env(PHYS_IP)/arm/tsmc/cln65lp/sc12_base_rvt/r0p0/gds2/sc12_cln65lp_base_rvt.gds2
set RF_16K_GDS2 $::env(SOCLABS_PROJECT_DIR)/memories/rf_16k/rf_16k.gds2
set RF_08K_GDS2 $::env(SOCLABS_PROJECT_DIR)/memories/rf_08k/rf_08k.gds2
set ROM_VIA_GDS2 $::env(SOCLABS_PROJECT_DIR)/memories/bootrom/rom_via.gds2
set_multi_cpu_usage -local_cpu 8
puts "Starting PnR Flow ..."
......@@ -37,58 +38,78 @@ source power_plan.tcl
### Power Route
source power_route.tcl
report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/1pre_place_nanosoc_imp_timing.rep
uniquify nanosoc_chip_pads -verbose
report_timing -late > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/1pre_place_nanosoc_imp_timing_late.rep
report_timing -early > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/1pre_place_nanosoc_imp_timing_early.rep
uniquify nanosoc_chip_pads -verbose
write_db nanosoc_chip_pads
### Placement
source place.tcl
report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/2post_place_nanosoc_imp_timing.rep
reorder_scan -skip_mode skipNone -allow_swapping false -keep_power_domain_ports true -clock_aware false
report_timing -late > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/2post_place_nanosoc_imp_timing_late.rep
report_timing -early > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/2post_place_nanosoc_imp_timing_early.rep
reorder_scan
write_db nanosoc_chip_pads
### CTS
source clock_tree_synthesis.tcl
reorder_scan -skip_mode skipNone -allow_swapping false -keep_power_domain_ports true -clock_aware true
reorder_scan -clock_aware true
report_timing -late > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/3post_clock_nanosoc_imp_timing_late.rep
report_timing -early > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/3post_clock_nanosoc_imp_timing_early.rep
report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/3post_clock_nanosoc_imp_timing.rep
### Add filler cells
eval_legacy { addFiller -cell FILL128_A12TR WELLANTENNATIEPW2_A12TR FILLTIE8_A12TR FILLTIE64_A12TR FILLTIE4_A12TR FILLTIE32_A12TR FILLTIE2_A12TR FILLTIE16_A12TR FILLTIE128_A12TR FILLCAPTIE8_A12TR -prefix FILLER -powerDomain ACCEL -doDRC }
eval_legacy { addFiller -cell WELLANTENNATIEPW2_A12TR FILLTIE8_A12TR FILLTIE64_A12TR FILLTIE4_A12TR FILLTIE32_A12TR FILLTIE2_A12TR FILLTIE16_A12TR FILLTIE128_A12TR FILLCAPTIE8_A12TR -prefix FILLER -powerDomain TOP -doDRC }
write_db nanosoc_chip_pads
### Add fillers
source filler.tcl
### Routing
source route.tcl
report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/4post_route_nanosoc_imp_timing.rep
report_timing -early > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/4post_route_nanosoc_imp_timing_early.rep
report_timing -late > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/4post_route_nanosoc_imp_timing_late.rep
check_antenna
write_db nanosoc_chip_pads
### Fill metal
set_metal_fill -layer M1 -opc_active_spacing 0.090 -border_spacing -0.001
set_metal_fill -layer M2 -opc_active_spacing 0.100 -border_spacing -0.001
set_metal_fill -layer M3 -opc_active_spacing 0.100 -border_spacing -0.001
set_metal_fill -layer M4 -opc_active_spacing 0.100 -border_spacing -0.001
set_metal_fill -layer M5 -opc_active_spacing 0.100 -border_spacing -0.001
set_metal_fill -layer M6 -opc_active_spacing 0.100 -border_spacing -0.001
set_metal_fill -layer M7 -opc_active_spacing 0.100 -border_spacing -0.001
set_metal_fill -layer M8 -opc_active_spacing 0.400 -border_spacing -0.001
set_metal_fill -layer M9 -opc_active_spacing 0.400 -border_spacing -0.001
set_metal_fill -layer AP -opc_active_spacing 2.000 -border_spacing -0.001
add_metal_fill -layers { M1 M2 M3 M4 M5 M6 M7 M8 M9 AP } -nets { VSSIO VSS VDDACC VDDIO VDD }
report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_imp_timing.rep
report_area > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_imp_area.rep
report_power > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_imp_power.rep
delete_routes -net VDDIO
delete_routes -net VSSIO
source place_bondpads.tcl
check_drc -out_file $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_imp_drc.rep
check_filler -out_file $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_imp_filler.rep
check_connectivity -out_file $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_imp_connectivity.rep
check_process_antenna -out_file $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_imp_antenna.rep
gui_show
report_timing -output_format gtd -max_paths 10000 -path_exceptions all -early > timing_full_default_early.mtarpt
report_timing -output_format gtd -max_paths 10000 -path_exceptions all -late > timing_full_default_late.mtarpt
set_analysis_view -setup [list typical_analysis_view] -hold [list typical_analysis_view]
report_timing -output_format gtd -max_paths 10000 -path_exceptions all -early > timing_full_typical_early.mtarpt
report_timing -output_format gtd -max_paths 10000 -path_exceptions all -late > timing_full_typical_late.mtarpt
set_analysis_view -setup [list default_analysis_view_setup typical_analysis_view] -hold [list default_analysis_view_hold typical_analysis_view]
write_stream $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/nanosoc.gds \
-map_file $::env(PHYS_IP)/arm/tsmc/cln65lp/arm_tech/r2p0/lef/1p9m_6x2z/tech.map \
-map_file /home/dwn1c21/SoC-Labs/util/PRTF_EDI_65nm_001_Cad_V24a/PR_tech/Cadence/GdsOutMap/PRTF_EDI_N65_gdsout_6X1Z1U.24a.map \
-lib_name DesignLib \
-merge [list ${SC_GDS2} ${RF_16K_GDS2} ${ROM_VIA_GDS2}]\
-output_macros -unit 2000 -mode all
-merge [list ${SC_GDS2} ${RF_16K_GDS2} ${RF_08K_GDS2} ${ROM_VIA_GDS2}]\
-output_macros -unit 1000 -mode all
report_area > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_imp_area.rep
report_power > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_imp_power.rep
report_timing -late > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_imp_timing_late.rep
report_timing -early > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_imp_timing_early.rep
set_analysis_view -setup [list typical_analysis_view] -hold [list typical_analysis_view]
report_timing -late > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_imp_timing_typical_late.rep
report_timing -early > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_imp_timing_typical_early.rep
set_analysis_view -setup [list default_analysis_view_setup typical_analysis_view] -hold [list default_analysis_view_hold typical_analysis_view]
write_netlist $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist_PnR/nanosoc_chip_pads_44pin.v
write_sdf -min_view default_analysis_view_hold -typical_view typical_analysis_view -max_view default_analysis_view_setup $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist_PnR/nanosoc_chip_pads_44pin.sdf
write_db nanosoc_chip_pads
ASIC/44pin/Cadence/scripts/power_plan.tcl
View file @ f783f487
......@@ -16,7 +16,8 @@ set_db add_rings_stacked_via_top_layer M8
set_db add_rings_stacked_via_bottom_layer M1
### Adding Rings
add_rings -nets {VDD VDDACC VSS} -type core_rings -follow core -layer {top M9 bottom M9 left M8 right M8} -width {top 3 bottom 3 left 3 right 3} -spacing {top 1 bottom 1 left 1 right 1} -offset {top 2 bottom 2 left 2 right 2} -center 0 -threshold 0 -jog_distance 0 -snap_wire_center_to_grid none
add_rings -nets {VDD VDDACC VSS} -type core_rings -follow core -layer {top M9 bottom M9 left M8 right M8} -width {top 3 bottom 3 left 3 right 3} -spacing {top 2 bottom 2 left 2 right 2} -offset {top 2 bottom 2 left 2 right 2} -center 0 -threshold 0 -jog_distance 0 -snap_wire_center_to_grid none
route_special -connect {pad_pin pad_ring} -layer_change_range { M1(1) AP(10) } -block_pin_target nearest_target -pad_pin_port_connect {all_port all_geom} -pad_pin_target nearest_target -allow_jogging 1 -crossover_via_layer_range { M1(1) AP(10) } -nets { VDD VSS VDDACC } -allow_layer_change 1 -pad_pin_width 6 -target_via_layer_range { M1(1) AP(10) }
### Adding Stripes
set_db add_stripes_ignore_block_check true
......@@ -38,7 +39,7 @@ set_db add_stripes_orthogonal_only true
set_db add_stripes_allow_jog { padcore_ring block_ring }
set_db add_stripes_skip_via_on_pin { standardcell }
set_db add_stripes_skip_via_on_wire_shape { noshape }
add_stripes -nets {VDD VDDACC VSS} -layer M6 -direction vertical -width 1.8 -spacing 0.8 -set_to_set_distance 58 -extend_to all_domains -start_from left -start_offset 39.5 -stop_offset 0 -switch_layer_over_obs false -max_same_layer_jog_length 2 -pad_core_ring_top_layer_limit AP -pad_core_ring_bottom_layer_limit M1 -block_ring_top_layer_limit AP -block_ring_bottom_layer_limit M1 -use_wire_group 0 -snap_wire_center_to_grid none
add_stripes -nets {VDD VDDACC VSS} -layer M6 -direction vertical -width 1.8 -spacing 0.8 -set_to_set_distance 60 -extend_to all_domains -start_from left -start_offset 39.5 -stop_offset 0 -switch_layer_over_obs false -max_same_layer_jog_length 2 -pad_core_ring_top_layer_limit AP -pad_core_ring_bottom_layer_limit M1 -block_ring_top_layer_limit AP -block_ring_bottom_layer_limit M1 -use_wire_group 0 -snap_wire_center_to_grid none
deselect_obj -all
......@@ -56,7 +57,7 @@ set_db add_stripes_trim_antenna_back_to_shape none
set_db add_stripes_spacing_type edge_to_edge
set_db add_stripes_spacing_from_block 0
set_db add_stripes_stripe_min_length stripe_width
set_db add_stripes_stacked_via_top_layer AP
set_db add_stripes_stacked_via_top_layer M9
set_db add_stripes_stacked_via_bottom_layer M4
set_db add_stripes_via_using_exact_crossover_size false
set_db add_stripes_split_vias false
......@@ -64,7 +65,7 @@ set_db add_stripes_orthogonal_only true
set_db add_stripes_allow_jog { padcore_ring block_ring }
set_db add_stripes_skip_via_on_pin { standardcell }
set_db add_stripes_skip_via_on_wire_shape { noshape }
add_stripes -nets {VDDACC VSS} -layer M9 -direction horizontal -width 1 -spacing 0.5 -set_to_set_distance 15 -over_power_domain 1 -start_from bottom -start_offset 0 -stop_offset 0 -switch_layer_over_obs false -max_same_layer_jog_length 2 -pad_core_ring_top_layer_limit AP -pad_core_ring_bottom_layer_limit M1 -block_ring_top_layer_limit AP -block_ring_bottom_layer_limit M1 -use_wire_group 0 -snap_wire_center_to_grid none
add_stripes -nets {VDDACC VSS} -layer M9 -direction horizontal -width 2 -spacing 2 -set_to_set_distance 20 -over_power_domain 1 -start_from bottom -start_offset 0 -stop_offset 0 -switch_layer_over_obs false -max_same_layer_jog_length 2 -pad_core_ring_top_layer_limit M9 -pad_core_ring_bottom_layer_limit M1 -block_ring_top_layer_limit M9 -block_ring_bottom_layer_limit M1 -use_wire_group 0 -snap_wire_center_to_grid none
deselect_obj -all
......
ASIC/44pin/Cadence/scripts/power_route.tcl
View file @ f783f487
......@@ -5,7 +5,7 @@
# Author : Srimanth Tenneti
##################################
route_special -connect {pad_pin pad_ring} -layer_change_range { M1(1) AP(10) } -block_pin_target nearest_target -pad_pin_port_connect {all_port all_geom} -pad_pin_target nearest_target -allow_jogging 1 -crossover_via_layer_range { M1(1) AP(10) } -nets { VDD VSS VDDACC } -allow_layer_change 1 -pad_pin_width 6 -target_via_layer_range { M1(1) AP(10) }
set_db route_special_via_connect_to_shape { padring stripe }
route_special -connect {block_pin core_pin floating_stripe} -layer_change_range { M1(1) AP(10) } -block_pin_target nearest_target -pad_pin_port_connect {all_port one_geom} -pad_pin_target nearest_target -core_pin_target first_after_row_end -floating_stripe_target {block_ring pad_ring ring stripe ring_pin block_pin followpin} -allow_jogging 1 -power_domains { ACCEL } -crossover_via_layer_range { M1(1) AP(10) } -nets { VDDACC VSS } -allow_layer_change 1 -block_pin use_lef -target_via_layer_range { M1(1) AP(10) }
route_special -connect {block_pin core_pin floating_stripe} -layer_change_range { M1(1) AP(10) } -block_pin_target nearest_target -pad_pin_port_connect {all_port one_geom} -pad_pin_target nearest_target -core_pin_target first_after_row_end -floating_stripe_target {block_ring pad_ring ring stripe ring_pin block_pin followpin} -allow_jogging 1 -power_domains { TOP } -crossover_via_layer_range { M1(1) AP(10) } -nets { VDD VSS } -allow_layer_change 1 -block_pin use_lef -target_via_layer_range { M1(1) AP(10) }
......
ASIC/44pin/Cadence/scripts/tieoff_exclude 0 → 100644
View file @ f783f487
uPAD_SE_I/IE
uPAD_SE_I/PE
uPAD_SE_I/DS
uPAD_SE_I/I
uPAD_SE_I/OEN
uPAD_CLK_I/IE
uPAD_CLK_I/PE
uPAD_CLK_I/DS
uPAD_CLK_I/I
uPAD_CLK_I/OEN
uPAD_TEST_I/IE
uPAD_TEST_I/PE
uPAD_TEST_I/DS
uPAD_TEST_I/I
uPAD_TEST_I/OEN
uPAD_NRST_I/IE
uPAD_NRST_I/PE
uPAD_NRST_I/DS
uPAD_NRST_I/I
uPAD_NRST_I/OEN
uPAD_SWDIO_IO/PE
uPAD_SWDIO_IO/DS
uPAD_SWDCK_I/IE
uPAD_SWDCK_I/PE
uPAD_SWDCK_I/DS
uPAD_SWDCK_I/I
uPAD_SWDCK_I/OEN
uPAD_P0_00/DS
uPAD_P0_01/DS
uPAD_P0_02/DS
uPAD_P0_03/DS
uPAD_P0_04/DS
uPAD_P0_05/DS
uPAD_P0_06/DS
uPAD_P0_07/DS
uPAD_P1_00/DS
uPAD_P1_01/DS
uPAD_P1_02/DS
uPAD_P1_03/DS
uPAD_P1_04/DS
uPAD_P1_05/DS
uPAD_P1_06/DS
uPAD_P1_07/DS
ASIC/44pin/Mentor/DRC 0 → 100644
View file @ f783f487
*drcRulesFile: /home/dwn1c21/SoC-Labs/phys_ip/TSMC/65/CMOS/LP/pdk/Calibre/drc/calibre.drc
*drcRulesFileLastLoad: 1708424374
*drcRunDir: ${SOCLABS_PROJECT_DIR}/imp/ASIC/nanosoc/DRC
*drcLayoutPaths: ${SOCLABS_PROJECT_DIR}/imp/ASIC/nanosoc/nanosoc.gds
*drcLayoutPrimary: nanosoc_chip_pads
*drcResultsFile: DRC_RES.db
*drcResultsCheckText: 1
*drcResultsCheckTextValue: ALL
*drcCellName: 0
*drcDRCMaxResultsAll: 1
*drcSummaryFile: DRC.rep
*drcActiveRecipe: Checks selected in the rules file
*drcUserRecipes: {{Checks selected in the rules file}}
*cmnResolution: 5
*cmnSlaveHosts: {use {}} {hostName {}} {cpuCount {}} {a32a64 {}} {rsh {}} {maxMem {}} {workingDir {}} {layerDir {}} {mgcLibPath {}} {launchName {}}
*cmnLSFSlaveTbl: {use 1} {totalCpus 1} {minCpus 1} {architecture {{}}} {minMemory {{}}} {resourceOptions {{}}} {submitOptions {{}}}
*cmnGridSlaveTbl: {use 1} {totalCpus 1} {minCpus 1} {architecture {{}}} {minMemory {{}}} {resourceOptions {{}}} {submitOptions {{}}}
ASIC/44pin/Mentor/ERC 0 → 100644
View file @ f783f487
*drcRulesFile: /home/dwn1c21/SoC-Labs/phys_ip/TSMC/65/CMOS/util/MAIN_DECK/CALIBRE_FLOW/nonUTM/DFM_LVS_RC_CAL_N65_ALRDL_noU_v16a.9m
*drcRulesFileLastLoad: 1708424374
*drcRunDir: ${SOCLABS_PROJECT_DIR}/imp/ASIC/nanosoc/DRC
*drcLayoutPaths: ${SOCLABS_PROJECT_DIR}/imp/ASIC/nanosoc/nanosoc_fanis_20_02_24.gds
*drcLayoutPrimary: nanosoc_chip_pads
*drcResultsFile: DRC_RES.db
*drcResultsCheckText: 1
*drcResultsCheckTextValue: ALL
*drcCellName: 0
*drcDRCMaxResultsAll: 1
*drcSummaryFile: DRC.rep
*drcActiveRecipe: Checks selected in the rules file (Modified)
*drcUserRecipes: {{Checks selected in the rules file (Modified)} {{group_unselect[1]} all {group_select[1]} rule_file}}
*cmnResolution: 5
*cmnSlaveHosts: {use {}} {hostName {}} {cpuCount {}} {a32a64 {}} {rsh {}} {maxMem {}} {workingDir {}} {layerDir {}} {mgcLibPath {}} {launchName {}}
*cmnLSFSlaveTbl: {use 1} {totalCpus 1} {minCpus 1} {architecture {{}}} {minMemory {{}}} {resourceOptions {{}}} {submitOptions {{}}}
*cmnGridSlaveTbl: {use 1} {totalCpus 1} {minCpus 1} {architecture {{}}} {minMemory {{}}} {resourceOptions {{}}} {submitOptions {{}}}
ASIC/44pin/Mentor/LVS 0 → 100644
View file @ f783f487
*lvsRulesFile: /home/dwn1c21/SoC-Labs/phys_ip/TSMC/65/CMOS/LP/pdk/Calibre/lvs/calibre.lvs
*lvsRunDir: ${SOCLABS_PROJECT_DIR}/imp/ASIC/nanosoc/LVS
*lvsLayoutPaths: ${SOCLABS_PROJECT_DIR}/imp/ASIC/nanosoc/nanosoc.gds
*lvsLayoutPrimary: nanosoc_chip_pads
*lvsSourcePath: ${SOCLABS_PROJECT_DIR}/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads_44pin.vp /research/AAA/phys_ip_library/arm/tsmc/cln65lp/sc12_base_lvt/r0p0/verilog/sc12_cln65lp_base_lvt.v
*lvsSourceSystem: VERILOG
*lvsSourcePrimary: nanosoc_chip_pads
*cmnV2LVS_LastTranslation: 1708338090
ASIC/constraints.sdc
View file @ f783f487
......@@ -16,48 +16,56 @@ set SWDCLK "swdclk";
set_units -time ns;
set_units -capacitance pF;
set EXTCLK_PERIOD 4.1666;
set SWDCLK_PERIOD 16.66666;
set EXTCLK_PERIOD 4.16667;
set SWDCLK_PERIOD [expr 4*$EXTCLK_PERIOD];
set CLK_ERROR 0.35; #Error calculated from worst case characteristics of CDCM61001 low-jitter oscillator chip at 250MHz
set INTER_CLOCK_UNCERTAINTY 0.1
create_clock -name "$EXTCLK" -period "$EXTCLK_PERIOD" -waveform "0 [expr $EXTCLK_PERIOD/2]" [get_ports CLK]
create_clock -name "$SWDCLK" -period "$SWDCLK_PERIOD" -waveform "0 [expr $SWDCLK_PERIOD/2]" [get_ports SWDCK]
set SKEW 0.800
set_clock_uncertainty [expr 0.17*$EXTCLK_PERIOD] [get_clocks $EXTCLK]
set_clock_uncertainty [expr 0.17*$SWDCLK_PERIOD] [get_clocks $SWDCLK]
set_clock_uncertainty $CLK_ERROR [get_clocks $EXTCLK]
set_clock_uncertainty $CLK_ERROR [get_clocks $SWDCLK]
set MINRISE 0.20
set MAXRISE 0.25
set MINFALL 0.20
set MAXFALL 0.25
set_clock_uncertainty -setup $INTER_CLOCK_UNCERTAINTY -rise_from [get_clocks $SWDCLK] -rise_to [get_clocks $EXTCLK]
set_clock_uncertainty -setup $INTER_CLOCK_UNCERTAINTY -rise_from [get_clocks $EXTCLK] -rise_to [get_clocks $SWDCLK]
set_clock_transition -rise -min $MINRISE [get_clocks $EXTCLK]
set_clock_transition -rise -max $MAXRISE [get_clocks $EXTCLK]
set_clock_transition -fall -min $MINFALL [get_clocks $EXTCLK]
set_clock_transition -fall -min $MINFALL [get_clocks $EXTCLK]
### Multicycle path through asynchronous clock domains
set_multicycle_path 2 -setup -end -from SWDCK -to CLK
set_multicycle_path 1 -hold -end -from SWDCK -to CLK
set_multicycle_path 2 -setup -end -from CLK -to SWDCK
set_multicycle_path 1 -hold -end -from CLK -to SWDCK
set_clock_transition -rise -min $MINRISE [get_clocks $SWDCLK]
set_clock_transition -rise -max $MAXRISE [get_clocks $SWDCLK]
set_clock_transition -fall -min $MINFALL [get_clocks $SWDCLK]
set_clock_transition -fall -min $MINFALL [get_clocks $SWDCLK]
set_false_path -hold -from CLK -to SWDCK
### Multicycle path through pads
#set_false_path -from uPAD_SWDIO_IO/* -to uPAD_SWDIO_IO/*
set_false_path -through uPAD_SWDIO_IO
set_false_path -through uPAD_P0_*
set_false_path -through uPAD_P1_*
#set_false_path -from uPAD_P0_*/* -to uPAD_P0_*/*
#set_false_path -from uPAD_P1_*/* -to uPAD_P1_*/*
set_multicycle_path 2 -through uPAD_SWDIO_IO
#set_false_path -through uPAD_P0_*
#set_false_path -through uPAD_P1_*
set_multicycle_path 2 -from uPAD_SWDIO_IO/I -to uPAD_SWDIO_IO/C
set_multicycle_path 2 -from uPAD_SWDIO_IO/IE -to uPAD_SWDIO_IO/C
set_multicycle_path 2 -from uPAD_SWDIO_IO/DS -to uPAD_SWDIO_IO/C
set_multicycle_path 2 -from uPAD_SWDIO_IO/OEN -to uPAD_SWDIO_IO/C
set_multicycle_path 2 -from uPAD_P0_*/I -to uPAD_P0_*/C
set_multicycle_path 2 -from uPAD_P0_*/IE -to uPAD_P0_*/C
set_multicycle_path 2 -from uPAD_P0_*/DS -to uPAD_P0_*/C
set_multicycle_path 2 -from uPAD_P0_*/OEN -to uPAD_P0_*/C
set_multicycle_path 2 -from uPAD_P1_*/I -to uPAD_P1_*/C
set_multicycle_path 2 -from uPAD_P1_*/IE -to uPAD_P1_*/C
set_multicycle_path 2 -from uPAD_P1_*/DS -to uPAD_P1_*/C
set_multicycle_path 2 -from uPAD_P1_*/OEN -to uPAD_P1_*/C
#### DELAY DEFINITION
set_input_delay -clock [get_clocks $EXTCLK] -add_delay 0.3 [get_ports NRST]
set_input_delay -clock [get_clocks $EXTCLK] -add_delay 0.3 [get_ports TEST]
set_input_delay -clock [get_clocks $EXTCLK] -add_delay 0.3 [get_ports P0]
set_input_delay -clock [get_clocks $EXTCLK] -add_delay 0.3 [get_ports P1]
set_input_delay -clock [get_clocks $SWDCLK] -add_delay 0.3 [get_ports SWDIO]
set_input_delay -clock [get_clocks $EXTCLK] -add_delay 0.1 [get_ports NRST]
set_input_delay -clock [get_clocks $EXTCLK] -add_delay 0.1 [get_ports TEST]
set_input_delay -clock [get_clocks $EXTCLK] -add_delay 0.1 [get_ports P0]
set_input_delay -clock [get_clocks $EXTCLK] -add_delay 0.1 [get_ports P1]
set_input_delay -clock [get_clocks $SWDCLK] -add_delay 0.1 [get_ports SWDIO]
set_max_capacitance 3 [all_outputs]
set_max_fanout 10 [all_inputs]
\ No newline at end of file
set_max_fanout 10 [all_inputs]
ASIC/nanosoc_chip_pads/tsmc65lp/nanosoc_chip_pads_44pin.v
View file @ f783f487
......@@ -44,6 +44,7 @@ module nanosoc_chip_pads (
inout wire VSS,
inout wire VDDACC,
input wire SE,
input wire CLK, // input
input wire TEST, // input
input wire NRST, // active low reset
......@@ -104,6 +105,8 @@ wire [15:0] soc_gpio_port1_o; // GPIO SOC trstate output
wire [15:0] soc_gpio_port1_e; // GPIO SOC tristate output enable
wire [15:0] soc_gpio_port1_z; // GPIO SOC tristate output hiz
wire pad_se_i;
// connect up high order GPIOs
assign soc_gpio_port0_i[15:GPIO_TIO] = pad_gpio_port0_i[15:GPIO_TIO];
assign pad_gpio_port0_o[15:GPIO_TIO] = soc_gpio_port0_o[15:GPIO_TIO];
......@@ -128,7 +131,7 @@ nanosoc_chip_cfg #(
,.pad_nrst_i (pad_nrst_i )
,.pad_test_i (pad_test_i )
// Alternate/reconfigurable IP and associated bidirectional I/O
,.pad_altin_i (pad_swdclk_i ) // SWCLK/UARTRXD/SCAN-ENABLE
,.pad_altin_i (pad_se_i ) // SWCLK/UARTRXD/SCAN-ENABLE
,.pad_altio_i (pad_swdio_i ) // SWDIO/UARTTXD tristate input
,.pad_altio_o (pad_swdio_o ) // SWDIO/UARTTXD trstate output
,.pad_altio_e (pad_swdio_e ) // SWDIO/UARTTXD tristate output enable
......@@ -180,7 +183,7 @@ nanosoc_chip_cfg #(
.VSS (VSS),
.VDDACC (VDDACC),
`endif
`ifdef ASIC_TEST_PORTS
//`ifdef ASIC_TEST_PORTS
.diag_mode (soc_diag_mode ),
.diag_ctrl (soc_diag_ctrl ),
.scan_mode (soc_scan_mode ),
......@@ -195,7 +198,7 @@ nanosoc_chip_cfg #(
.uart_rxd_i (soc_uart_rxd_i ), // UART RXD
.uart_txd_o (soc_uart_txd_o ), // UART TXD
.swd_mode (soc_swd_mode ), // SWD mode
`endif
//`endif
.clk_i(pad_clk_i),
.test_i(soc_scan_mode),
.nrst_i(soc_nreset),
......@@ -211,7 +214,7 @@ nanosoc_chip_cfg #(
.swdio_o(soc_swd_dio_o),
.swdio_e(soc_swd_dio_e),
.swdio_z(soc_swd_dio_z),
.swdclk_i(soc_swd_clk_i)
.swdclk_i(pad_swdclk_i)
);
......@@ -224,9 +227,9 @@ nanosoc_chip_cfg #(
PVDD2CDG uPAD_VDDIO_0(
.VDDPST(VDDIO)
);
PVDD2CDG uPAD_VDDIO_1(
.VDDPST(VDDIO)
);
//PVDD2CDG uPAD_VDDIO_1(
// .VDDPST(VDDIO)
// );
PVDD2CDG uPAD_VDDIO_2(
.VDDPST(VDDIO)
);
......@@ -234,11 +237,11 @@ PVDD2POC uPAD_VDDIO_3(
.VDDPST(VDDIO)
);
PVSS3CDG uPAD_VSSIO_0(
.VSS(VSS)
PVSS2CDG uPAD_VSSIO_0(
.VSSPST(VSSIO)
);
PVSS3CDG uPAD_VSSIO_1(
.VSS(VSS)
PVSS2CDG uPAD_VSSIO_1(
.VSSPST(VSSIO)
);
// Core power supplies
......@@ -256,16 +259,16 @@ PVDD1CDG uPAD_VDD_3(
.VDD(VDD)
);
PVSS3CDG uPAD_VSS_0(
PVSS1CDG uPAD_VSS_0(
.VSS(VSS)
);
PVSS3CDG uPAD_VSS_1(
PVSS1CDG uPAD_VSS_1(
.VSS(VSS)
);
PVSS3CDG uPAD_VSS_2(
PVSS1CDG uPAD_VSS_2(
.VSS(VSS)
);
PVSS3CDG uPAD_VSS_3(
PVSS1CDG uPAD_VSS_3(
.VSS(VSS)
);
// Accelerator Power supplies
......@@ -281,6 +284,17 @@ PVDD1CDG uPAD_VDDACC_2(
// Clock, Reset and Serial Wire Debug ports
PRDW0408SCDG uPAD_SE_I (
.IE(tiehi),
.C(pad_se_i),
.PE(tielo),
.DS(tielo),
.I(tielo),
.OEN(tiehi),
.PAD(SE)
);
PRDW0408SCDG uPAD_CLK_I (
.IE(tiehi),
.C(pad_clk_i),
......