ASIC flow correct cup and bondpad versions

ASIC/44pin/Cadence/scripts/design_import.tcl

@@ -17,8 +17,8 @@ read_mmmc nanosoc.mmmc
 set TECH_LEF /home/dwn1c21/SoC-Labs/util/PRTF_EDI_65nm_001_Cad_V24a/PRTF_EDI_N65_9M_6X1Z1U_RDL.24a.tlef
 #$::env(PHYS_IP)/arm/tsmc/cln65lp/arm_tech/r2p0/lef/1p9m_6x2z/sc12_tech.lef
 set BASE_LEF $::env(PHYS_IP)/arm/tsmc/cln65lp/sc12_base_rvt/r0p0/lef/sc12_cln65lp_base_rvt.lef
-set IO_PAD_LEF /home/dwn1c21/SoC-Labs/phys_ip/tsmc/cln65lp/Backend/lef/tpbn65v_9lm.lef
-set IO_PAD_DRIVER_LEF /home/dwn1c21/SoC-Labs/phys_ip/tsmc/cln65lp/Backend/lef/tpdn65lpnv2od3_9lm.lef
+set IO_PAD_LEF /home/dwn1c21/SoC-Labs/phys_ip/TSMC/65/iolib/tpbn65v_200b_FE/TSMCHOME/digital/Back_End/lef/tpbn65v_200b/cup/9m/9M_6X1Z1U/lef/tpbn65v_9lm.lef
+set IO_PAD_DRIVER_LEF /home/dwn1c21/SoC-Labs/phys_ip/TSMC/65/CMOS/LP/IO2.5V/iolib/linear/tpdn65lpnv2od3_200a_FE/TSMCHOME/digital/Back_End/lef/tpdn65lpnv2od3_140b/mt_2/9lm/lef/tpdn65lpnv2od3_9lm.lef
 
 
 # !! THESE SHOULD BE CORRECT FOR ANY ENVIRONMENT AS THEY ARE GENERATED BY MAKEFILE

ASIC/44pin/Cadence/scripts/nanosoc.mmmc

@@ -5,7 +5,7 @@ set tech_path ${phys_lib}/arm/tsmc/cln65lp/arm_tech/r2p0
 set ram_path /home/dwn1c21/SoC-Labs/TAPEOUT_feb2024/Fanis/fast-knn-accelerator-project/memories/rf_16k/
 set ram_08k_path /home/dwn1c21/SoC-Labs/TAPEOUT_feb2024/Fanis/fast-knn-accelerator-project/memories/rf_08k/
 set rom_path /home/dwn1c21/SoC-Labs/TAPEOUT_feb2024/Fanis/fast-knn-accelerator-project/memories/bootrom/
-set IO_driver_path /home/dwn1c21/SoC-Labs/phys_ip/tsmc/cln65lp/Front_End/timing_power_noise/NLDM/tpdn65lpnv2od3_200a/
+set IO_driver_path /home/dwn1c21/SoC-Labs/phys_ip/TSMC/65/CMOS/LP/IO2.5V/iolib/linear/tpdn65lpnv2od3_200a_FE/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tpdn65lpnv2od3_200a/
 
 create_library_set -name default_libset_max\
    -timing\
@@ -21,7 +21,7 @@ create_library_set -name default_libset_min\
 
 create_library_set -name typical_libset\
    -timing\
-    [list ${base_path}/lib/sc12_cln65lp_base_rvt_tt_typical_max_1p20v_25c.lib ${ram_path}/rf_16k_tt_1p20v_1p20v_25c.lib ${ram_08k_path}/rf_08k_tt_1p20v_1p20v_25c.lib ${rom_path}/rom_via_tt_1p20v_1p20v_25c.lib ${IO_driver_path}/tpdn65lpnv2od3bc.lib] \
+    [list ${base_path}/lib/sc12_cln65lp_base_rvt_tt_typical_max_1p20v_25c.lib ${ram_path}/rf_16k_tt_1p20v_1p20v_25c.lib ${ram_08k_path}/rf_08k_tt_1p20v_1p20v_25c.lib ${rom_path}/rom_via_tt_1p20v_1p20v_25c.lib ${IO_driver_path}/tpdn65lpnv2od3tc.lib] \
    -si\
     [list ${base_path}/celtic/sc12_cln65lp_base_rvt_tt_typical_max_1p20v_25c.cdB]
 

ASIC/44pin/Cadence/scripts/pnr_flow.tcl

@@ -72,36 +72,27 @@ add_fillers -base_cells [list FILL128_A12TR WELLANTENNATIEPW2_A12TR FILLTIE8_A12
 add_fillers -base_cells [list FILL128_A12TR WELLANTENNATIEPW2_A12TR FILLTIE8_A12TR FILLTIE64_A12TR FILLTIE4_A12TR FILLTIE32_A12TR FILLTIE2_A12TR FILLTIE16_A12TR FILLTIE128_A12TR FILLCAPTIE8_A12TR] -prefix FILLER -power_domain TOP -check_drc true
 add_fillers -base_cells [list FILL128_A12TR WELLANTENNATIEPW2_A12TR FILLTIE8_A12TR FILLTIE64_A12TR FILLTIE4_A12TR FILLTIE32_A12TR FILLTIE2_A12TR FILLTIE16_A12TR FILLTIE128_A12TR FILLCAPTIE8_A12TR] -prefix FILLER -power_domain ACCEL -check_drc true -fix_drc
 add_fillers -base_cells [list FILL128_A12TR WELLANTENNATIEPW2_A12TR FILLTIE8_A12TR FILLTIE64_A12TR FILLTIE4_A12TR FILLTIE32_A12TR FILLTIE2_A12TR FILLTIE16_A12TR FILLTIE128_A12TR FILLCAPTIE8_A12TR] -prefix FILLER -power_domain TOP -check_drc true -fix_drc
-
+delete_routes -net VDDIO
 source place_bondpads.tcl
 
-### Fill metal
-set_metal_fill -layer M1 -opc_active_spacing 0.090 -border_spacing -0.001
-set_metal_fill -layer M2 -opc_active_spacing 0.100 -border_spacing -0.001
-set_metal_fill -layer M3 -opc_active_spacing 0.100 -border_spacing -0.001
-set_metal_fill -layer M4 -opc_active_spacing 0.100 -border_spacing -0.001
-set_metal_fill -layer M5 -opc_active_spacing 0.100 -border_spacing -0.001
-set_metal_fill -layer M6 -opc_active_spacing 0.100 -border_spacing -0.001
-set_metal_fill -layer M7 -opc_active_spacing 0.100 -border_spacing -0.001
-set_metal_fill -layer M8 -opc_active_spacing 0.400 -border_spacing -0.001
-set_metal_fill -layer M9 -opc_active_spacing 0.400 -border_spacing -0.001
-set_metal_fill -layer AP -opc_active_spacing 2.000 -border_spacing -0.001
-add_metal_fill -layers { M1 M2 M3 M4 M5 M6 M7 M8 M9 AP } -nets { VSSIO VSS VDDACC VDDIO VDD }
-
-
-report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_imp_timing.rep
-report_area > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_imp_area.rep
-report_power > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_imp_power.rep
-
 gui_show 
 
 write_stream $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/nanosoc.gds \
     -map_file /home/dwn1c21/SoC-Labs/util/PRTF_EDI_65nm_001_Cad_V24a/PR_tech/Cadence/GdsOutMap/PRTF_EDI_N65_gdsout_6X1Z1U.24a.map \
     -lib_name DesignLib \
     -merge [list ${SC_GDS2} ${RF_16K_GDS2} ${RF_08K_GDS2} ${ROM_VIA_GDS2}]\
-    -output_macros -unit 1000 -mode all -uniquify_cell_names 
+    -output_macros -unit 1000 -mode all  
 
 
 write_netlist $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist_PnR/nanosoc_chip_pads_44pin.v
 write_sdf $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist_PnR/nanosoc_chip_pads_44pin.sdf
+
+
+report_area > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_imp_area.rep
+report_power > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_imp_power.rep
+
+report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_imp_timing.rep
+set_analysis_view -setup [list typical_analysis_view] -hold [list typical_analysis_view]
+report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/nanosoc_imp_timing_typical.rep
+
 write_db nanosoc_chip_pads