Update PnR flow inc Tie offs

ASIC/44pin/Cadence/scripts/nanosoc.mmmc

@@ -19,10 +19,18 @@ create_library_set -name default_libset_min\
    -si\
     [list ${base_path}/celtic/sc12_cln65lp_base_rvt_ff_typical_min_1p32v_m40c.cdB]
 
+create_library_set -name typical_libset\
+   -timing\
+    [list ${base_path}/lib/sc12_cln65lp_base_rvt_tt_typical_max_1p20v_25c.lib ${ram_path}/rf_16k_tt_1p20v_1p20v_25c.lib ${ram_08k_path}/rf_08k_tt_1p20v_1p20v_25c.lib ${rom_path}/rom_via_tt_1p20v_1p20v_25c.lib ${IO_driver_path}/tpdn65lpnv2od3bc.lib] \
+   -si\
+    [list ${base_path}/celtic/sc12_cln65lp_base_rvt_tt_typical_max_1p20v_25c.cdB]
+
 create_timing_condition -name default_mapping_tc_2\
    -library_sets [list default_libset_min]
 create_timing_condition -name default_mapping_tc_1\
    -library_sets [list default_libset_max]
+create_timing_condition -name typical_mapping\
+   -library_sets [list typical_libset]
 
 create_rc_corner -name default_rc_corner_worst\
    -pre_route_res 1\
@@ -69,6 +77,10 @@ create_delay_corner -name default_delay_corner_min\
    -timing_condition default_mapping_tc_2\
    -rc_corner default_rc_corner_best
 
+create_delay_corner -name typical_delay_corner\
+   -timing_condition typical_mapping\
+   -rc_corner default_rc_corner_typical
+
 create_constraint_mode -name default_constraint_mode\
    -sdc_files\
     [list ../../../constraints.sdc]
@@ -81,5 +93,6 @@ create_analysis_view -name default_analysis_view_hold -constraint_mode default_c
 create_analysis_view -name typical_analysis_view_setup -constraint_mode default_constraint_mode -delay_corner default_delay_corner_ocv
 create_analysis_view -name typical_analysis_view_hold -constraint_mode default_constraint_mode -delay_corner default_delay_corner_ocv
 
+create_analysis_view -name typical_analysis_view -constraint_mode default_constraint_mode -delay_corner typical_delay_corner
 
 set_analysis_view -setup [list default_analysis_view_setup] -hold [list default_analysis_view_hold]

ASIC/44pin/Cadence/scripts/place.tcl

@@ -19,3 +19,6 @@ place_design
 
 ### Delay Calculation 
 write_sdf design.sdf -ideal_clock_network 
+set_db add_tieoffs_max_fanout 10
+add_tieoffs -lib_cell {TIELO_X1M_A12TR TIEHI_X1M_A12TR} -prefix LTIE -power_domain TOP
+add_tieoffs -lib_cell {TIELO_X1M_A12TR TIEHI_X1M_A12TR} -prefix LTIE -power_domain ACCEL

ASIC/44pin/Cadence/scripts/pnr_flow.tcl

@@ -14,6 +14,7 @@
 
 set SC_GDS2 $::env(PHYS_IP)/arm/tsmc/cln65lp/sc12_base_rvt/r0p0/gds2/sc12_cln65lp_base_rvt.gds2
 set RF_16K_GDS2 $::env(SOCLABS_PROJECT_DIR)/memories/rf_16k/rf_16k.gds2
+set RF_08K_GDS2 $::env(SOCLABS_PROJECT_DIR)/memories/rf_08k/rf_08k.gds2
 set ROM_VIA_GDS2 $::env(SOCLABS_PROJECT_DIR)/memories/bootrom/rom_via.gds2
 
 
@@ -39,13 +40,13 @@ source power_route.tcl
 
 report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/1pre_place_nanosoc_imp_timing.rep
 uniquify nanosoc_chip_pads -verbose
-
+write_db nanosoc_chip_pads
 ### Placement 
 source place.tcl 
 
 report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/2post_place_nanosoc_imp_timing.rep
 reorder_scan -skip_mode skipNone -allow_swapping false -keep_power_domain_ports true -clock_aware false
-
+write_db nanosoc_chip_pads
 
 ### CTS 
 source clock_tree_synthesis.tcl 
@@ -56,7 +57,7 @@ report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/3post_clock
 ### Add filler cells
 eval_legacy { addFiller -cell FILL128_A12TR WELLANTENNATIEPW2_A12TR FILLTIE8_A12TR FILLTIE64_A12TR FILLTIE4_A12TR FILLTIE32_A12TR FILLTIE2_A12TR FILLTIE16_A12TR FILLTIE128_A12TR FILLCAPTIE8_A12TR -prefix FILLER -powerDomain ACCEL -doDRC }
 eval_legacy { addFiller -cell WELLANTENNATIEPW2_A12TR FILLTIE8_A12TR FILLTIE64_A12TR FILLTIE4_A12TR FILLTIE32_A12TR FILLTIE2_A12TR FILLTIE16_A12TR FILLTIE128_A12TR FILLCAPTIE8_A12TR -prefix FILLER -powerDomain TOP -doDRC }
-
+write_db nanosoc_chip_pads
 
 ### Routing 
 source route.tcl 
@@ -64,7 +65,7 @@ source route.tcl
 report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/4post_route_nanosoc_imp_timing.rep
 
 check_antenna
-
+write_db nanosoc_chip_pads
 ### Fill metal
 set_metal_fill -layer M1 -opc_active_spacing 0.090 -border_spacing -0.001
 set_metal_fill -layer M2 -opc_active_spacing 0.100 -border_spacing -0.001
@@ -88,7 +89,10 @@ gui_show
 write_stream $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/nanosoc.gds \
     -map_file $::env(PHYS_IP)/arm/tsmc/cln65lp/arm_tech/r2p0/lef/1p9m_6x2z/tech.map \
     -lib_name DesignLib \
-    -merge [list ${SC_GDS2} ${RF_16K_GDS2} ${ROM_VIA_GDS2}]\
+    -merge [list ${SC_GDS2} ${RF_16K_GDS2} ${RF_08K_GDS2} ${ROM_VIA_GDS2}]\
     -output_macros -unit 2000 -mode all
 
 
+write_netlist $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist_PnR/nanosoc_chip_pads_44pin.v
+write_sdf $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist_PnR/nanosoc_chip_pads_44pin.sdf
+write_db nanosoc_chip_pads

ASIC/44pin/Cadence/scripts/power_plan.tcl

@@ -38,7 +38,7 @@ set_db add_stripes_orthogonal_only true
 set_db add_stripes_allow_jog { padcore_ring  block_ring }
 set_db add_stripes_skip_via_on_pin {  standardcell }
 set_db add_stripes_skip_via_on_wire_shape {  noshape   }
-add_stripes -nets {VDD VDDACC VSS} -layer M6 -direction vertical -width 1.8 -spacing 0.8 -set_to_set_distance 58 -extend_to all_domains -start_from left -start_offset 39.5 -stop_offset 0 -switch_layer_over_obs false -max_same_layer_jog_length 2 -pad_core_ring_top_layer_limit AP -pad_core_ring_bottom_layer_limit M1 -block_ring_top_layer_limit AP -block_ring_bottom_layer_limit M1 -use_wire_group 0 -snap_wire_center_to_grid none
+add_stripes -nets {VDD VDDACC VSS} -layer M6 -direction vertical -width 1.8 -spacing 0.8 -set_to_set_distance 56 -extend_to all_domains -start_from left -start_offset 39.5 -stop_offset 0 -switch_layer_over_obs false -max_same_layer_jog_length 2 -pad_core_ring_top_layer_limit AP -pad_core_ring_bottom_layer_limit M1 -block_ring_top_layer_limit AP -block_ring_bottom_layer_limit M1 -use_wire_group 0 -snap_wire_center_to_grid none
 
 deselect_obj -all
 

ASIC/constraints.sdc

@@ -16,8 +16,8 @@ set SWDCLK "swdclk";
 set_units -time ns;
 
 set_units -capacitance pF;
-set EXTCLK_PERIOD 4.1666;
-set SWDCLK_PERIOD 16.66666;
+set EXTCLK_PERIOD 4.1667;
+set SWDCLK_PERIOD [expr 4*$EXTCLK_PERIOD];
 
 create_clock -name "$EXTCLK" -period "$EXTCLK_PERIOD" -waveform "0 [expr $EXTCLK_PERIOD/2]" [get_ports CLK]
 create_clock -name "$SWDCLK" -period "$SWDCLK_PERIOD" -waveform "0 [expr $SWDCLK_PERIOD/2]" [get_ports SWDCK]
@@ -45,6 +45,7 @@ set_clock_transition -fall -min $MINFALL [get_clocks $SWDCLK]
 
 #set_false_path -from uPAD_SWDIO_IO/* -to uPAD_SWDIO_IO/*
 set_false_path -through uPAD_SWDIO_IO
+set_multicycle_path -through uPAD_SWDIO_IO
 set_false_path -through uPAD_P0_*
 set_false_path -through uPAD_P1_*
 #set_false_path -from uPAD_P0_*/*  -to uPAD_P0_*/*

ASIC/nanosoc_chip_pads/tsmc65lp/nanosoc_chip_pads_44pin.v

@@ -180,7 +180,7 @@ nanosoc_chip_cfg #(
   .VSS        (VSS),
   .VDDACC     (VDDACC),
 `endif
-`ifdef ASIC_TEST_PORTS
+//`ifdef ASIC_TEST_PORTS
   .diag_mode   (soc_diag_mode     ),
   .diag_ctrl   (soc_diag_ctrl     ),
   .scan_mode   (soc_scan_mode     ),
@@ -195,7 +195,7 @@ nanosoc_chip_cfg #(
   .uart_rxd_i  (soc_uart_rxd_i    ), // UART RXD
   .uart_txd_o  (soc_uart_txd_o    ), // UART TXD
   .swd_mode    (soc_swd_mode      ),    // SWD mode
-`endif
+//`endif
   .clk_i(pad_clk_i),
   .test_i(soc_scan_mode),
   .nrst_i(soc_nreset),