remove ASIC_TEST_PORTS dependence at chip level

nanosoc/nanosoc_chip/chip/verilog/nanosoc_chip.v

@@ -19,7 +19,7 @@ module nanosoc_chip #(
   inout  wire          VSS,
   inout  wire          VDDACC,
 `endif
-`ifdef ASIC_TEST_PORTS
+//`ifdef ASIC_TEST_PORTS
   input  wire                diag_mode,
   input  wire                diag_ctrl,
   input  wire                scan_mode,
@@ -34,7 +34,7 @@ module nanosoc_chip #(
   input  wire                uart_rxd_i,  // UART RXD
   output wire                uart_txd_o,  // UART TXD
   input  wire                swd_mode,    // SWD mode
-`endif
+//`endif
   input  wire          clk_i,
 //  output wire          xtal_clk_o,
   input  wire          test_i,
@@ -111,18 +111,18 @@ module nanosoc_chip #(
   
   assign PLL_CLK    = clk_i; // Default to no PLL
 
-`ifdef ASIC_TEST_PORTS
+//`ifdef ASIC_TEST_PORTS
   assign SYS_SCANENABLE   = scan_enable;
   assign SYS_TESTMODE     = scan_mode;
   assign SYS_SCANINHCLK   = 1'b1;
 ///  assign scan_out         = scan_in;
   assign bist_out         = bist_in;
 ///  assign uart_txd_o       = uart_rxd_i;
-`else
-  assign SYS_SCANENABLE   = test_i & swdio_i; 
-  assign SYS_TESTMODE     = test_i;   
-  assign SYS_SCANINHCLK   = 1'b1;
-`endif
+//`else
+//  assign SYS_SCANENABLE   = test_i & swdio_i; 
+//  assign SYS_TESTMODE     = test_i;   
+//  assign SYS_SCANINHCLK   = 1'b1;
+//`endif
 
   //--------------------------
   // Clock Wiring
@@ -171,7 +171,7 @@ module nanosoc_chip #(
   assign        p1_e[3] = 1'b1; 
   assign        p1_z[3] = 1'b0;
 
-  assign        P1_IN_MUX[4] = (alt_mode) ? uart_txd_i : p1_i[4]; // RXD2
+  assign        P1_IN_MUX[4] = (alt_mode) ? uart_rxd_i : p1_i[4]; // RXD2
   assign        uart_txd_o = P1_OUT_MUX[5]; // TXD2
 
   assign        P1_IN_MUX[15:5] = p1_i[15:5]; // IO MUX controlled bidirectionals

nanosoc/nanosoc_chip/pads/glib/verilog/nanosoc_chip_pads.v

@@ -182,7 +182,7 @@ nanosoc_chip_cfg #(
   .VSS         (VSS),
   .VDDACC      (VDDACC),
 `endif
-`ifdef ASIC_TEST_PORTS
+//`ifdef ASIC_TEST_PORTS
   .diag_mode   (soc_diag_mode     ),
   .diag_ctrl   (soc_diag_ctrl     ),
   .scan_mode   (soc_scan_mode     ),
@@ -193,11 +193,11 @@ nanosoc_chip_cfg #(
   .bist_enable (soc_bist_enable   ),
   .bist_in     (soc_bist_in       ), // soc bist control inputs
   .bist_out    (soc_bist_out      ),       // soc test status outputs
-  .alt_mode    (soc_alt_mode      )// ALT MODE = UART
-  .uart_rxd_i  (soc_uart_rxd_i    ) // UART RXD
-  .uart_txd_o  (soc_uart_txd_o    ) // UART TXD
+  .alt_mode    (soc_alt_mode      ),// ALT MODE = UART
+  .uart_rxd_i  (soc_uart_rxd_i    ), // UART RXD
+  .uart_txd_o  (soc_uart_txd_o    ), // UART TXD
   .swd_mode    (soc_swd_mode      ),    // SWD mode
-`endif
+//`endif
   .clk_i       (pad_clk_i),
   .test_i      (soc_scan_mode), //(test_i),
   .nrst_i      (soc_nreset), //(nrst_i),