flows/makefile.asic

@@ -38,7 +38,8 @@ MEMORIES_DIR		:= $(SOCLABS_PROJECT_DIR)/memories
 RF_16K_SPEC_FILE	:= $(SOCLABS_NANOSOC_TECH_DIR)/ASIC/rf_16k.spec
 RF_08K_SPEC_FILE		:= $(SOCLABS_NANOSOC_TECH_DIR)/ASIC/rf_08k.spec
 ROM_SPEC_FILE		:= $(SOCLABS_NANOSOC_TECH_DIR)/ASIC/rom_via.spec
-BOOTROM_BIN_FILE	:= $(SOCLABS_PROJECT_DIR)/system/src/bootrom/bintxt/bootrom.bintxt
+BOOTROM_BIN_FILE_IN := $(SOCLABS_PROJECT_DIR)/system/src/bootrom/bintxt/bootrom.bintxt
+BOOTROM_BIN_FILE	:= $(SOCLABS_PROJECT_DIR)/system/src/bootrom/bintxt/bootrom.rcf
 RF_16K_DIR			:= $(MEMORIES_DIR)/rf_16k
 RF_08K_DIR			:= $(MEMORIES_DIR)/rf_08k
 ROM_DIR 			:= $(MEMORIES_DIR)/bootrom
@@ -77,6 +78,7 @@ gen_memories: bootrom
 	@mkdir -p $(RF_16K_DIR)
 	@mkdir -p $(RF_08K_DIR)
 	@mkdir -p $(ROM_DIR)
+	cp $(BOOTROM_BIN_FILE_IN) $(BOOTROM_BIN_FILE)
 	echo "Generating register file memory libraries"
 	echo "16K RF"
 	cd $(RF_16K_DIR); $(PHYS_IP)/arm/tsmc/cln65lp/rf_sp_hdf_hvt_rvt/r0p0/bin/rf_sp_hdf_hvt_rvt all -spec $(RF_16K_SPEC_FILE);
@@ -93,11 +95,17 @@ gen_memories: bootrom
 convert_mem_to_db: 
 	lc_shell -no_log -f  $(NANOSOC_SYNTH_DIR)/synopsys_lib_conversion.tcl
 
-syn_genus: 
+syn_genus_44pin: 
 	@mkdir -p $(REPORTS_FOLDER)
 	@mkdir -p $(NETLIST_FOLDER)
 	@mkdir -p $(SYN_LOGS)
-	cd $(NANOSOC_SYNTH_DIR)/Cadence/Genus; genus -f $(NANOSOC_SYNTH_DIR)/Cadence/Genus/genus.tcl -log $(SYN_LOGS)/nanosoc_synth_genus.log
+	cd $(NANOSOC_SYNTH_DIR)/44pin/Cadence/scripts; genus -f $(NANOSOC_SYNTH_DIR)/44pin/Cadence/scripts/genus.tcl -log $(SYN_LOGS)/nanosoc_synth_genus.log
+
+syn_genus_44pin_noDFT: 
+	@mkdir -p $(REPORTS_FOLDER)
+	@mkdir -p $(NETLIST_FOLDER)
+	@mkdir -p $(SYN_LOGS)
+	cd $(NANOSOC_SYNTH_DIR)/44pin/Cadence/scripts; genus -f $(NANOSOC_SYNTH_DIR)/44pin/Cadence/scripts/genus_nodft.tcl -log $(SYN_LOGS)/nanosoc_synth_genus_noDFT.log
 
 syn_dc:
 	@mkdir -p $(REPORTS_FOLDER)

nanosoc/nanosoc_chip/pads/glib/verilog/nanosoc_chip_pads.v

@@ -43,7 +43,8 @@ module nanosoc_chip_pads (
   inout  wire          VDD,
   inout  wire          VSS,
   inout  wire          VDDACC,
-`endif
+`endif   
+  input  wire          SE,
   inout  wire          CLK, // input
   inout  wire          TEST, // output
   inout  wire          NRST,  // active low reset
@@ -103,6 +104,9 @@ wire [15:0] soc_gpio_port1_o; // GPIO SOC trstate output
 wire [15:0] soc_gpio_port1_e; // GPIO SOC tristate output enable
 wire [15:0] soc_gpio_port1_z; // GPIO SOC tristate output hiz
 
+wire pad_se_i;
+
+
 // connect up high order GPIOs
 assign soc_gpio_port0_i[15:GPIO_TIO] = pad_gpio_port0_i[15:GPIO_TIO];
 assign pad_gpio_port0_o[15:GPIO_TIO] = soc_gpio_port0_o[15:GPIO_TIO];
@@ -126,7 +130,7 @@ nanosoc_chip_cfg #(
   ,.pad_nrst_i       (pad_nrst_i        )
   ,.pad_test_i       (pad_test_i        )
   // Alternate/reconfigurable IP and associated bidirectional I/O
-  ,.pad_altin_i      (pad_swdclk_i      )  // SWCLK/UARTRXD/SCAN-ENABLE
+  ,.pad_altin_i      (pad_se_i      )  // SWCLK/UARTRXD/SCAN-ENABLE
   ,.pad_altio_i      (pad_swdio_i       )  // SWDIO/UARTTXD tristate input
   ,.pad_altio_o      (pad_swdio_o       )  // SWDIO/UARTTXD trstate output
   ,.pad_altio_e      (pad_swdio_e       )  // SWDIO/UARTTXD tristate output enable
@@ -213,7 +217,7 @@ nanosoc_chip_cfg #(
   .swdio_o     (soc_swd_dio_o),
   .swdio_e     (soc_swd_dio_e),
   .swdio_z     (soc_swd_dio_z),
-  .swdclk_i    (soc_swd_clk_i)
+  .swdclk_i    (pad_swdclk_i)
   );
 
 
@@ -250,6 +254,13 @@ PAD_VDDSOC uPAD_VDDACC_1(
 
 // Clock, Reset and Serial Wire Debug ports
 
+PAD_INOUT8MA_NOE uPAD_SE_I (
+   .PAD (SE), 
+   .O   (tielo),
+   .I   (pad_se_i), 
+   .NOE (tiehi)
+   );
+
 PAD_INOUT8MA_NOE uPAD_CLK_I (
    .PAD (CLK), 
    .O   (tielo),

verif/tb/verilog/nanosoc_tb.v

@@ -135,6 +135,7 @@ initial begin
   .VSS        (VSS),
   .VDDACC     (VDDACC),
 `endif
+  .SE         (1'b0),
   .CLK        (CLK),  // input
   .TEST       (TEST),  // input
   .NRST       (NRST),   // active low reset
@@ -153,6 +154,7 @@ initial begin
   .VSS        (VSS),
   .VDDACC     (VDDACC),
 `endif
+  .SE         (1'b0),
   .CLK        (CLK),  // input
   .TEST       (TEST),  // input
   .NRST       (NRST),   // active low reset

verif/trace/verilog/nanosoc_axi_stream_io_8_txd_from_file.v

@@ -18,7 +18,8 @@
 module nanosoc_axi_stream_io_8_txd_from_file
   #(parameter TXDFILENAME = "adp.cmd",
     parameter CODEFILENAME = "image.hex",
-    parameter VERBOSE = 0)
+    parameter VERBOSE = 0,
+    parameter FAST_LOAD = 1)
   (
   input  wire  aclk,
   input  wire  aresetn,
@@ -104,21 +105,31 @@ localparam BUFSIZE = (64 * 1024);
        adpbuf[ 9] = "0"; //
        adpbuf[10] = "0"; //
        adpbuf[11] = 8'h0a; // newline
-       adpbuf[12] = "U"; // set upload filesize (N bytes)
-       adpbuf[13] = " "; // only up to 1Mbyte for now!
-       adpbuf[14] = FNmap_hex_digit(codesize[19:16]); //
-       adpbuf[15] = FNmap_hex_digit(codesize[15:12]); //
-       adpbuf[16] = FNmap_hex_digit(codesize[11: 8]); //
-       adpbuf[17] = FNmap_hex_digit(codesize[ 7: 4]); //
-       adpbuf[18] = FNmap_hex_digit(codesize[ 3: 0]); //
-       adpbuf[19] = 8'h0a; // newline
-       $readmemh(CODEFILENAME, adpbuf, 20);
-       adpbuf[clen+20] = "C"; // control
-       adpbuf[clen+21] = " ";
-       adpbuf[clen+22] = "2"; // (gpio bit set)
-       adpbuf[clen+23] = "0";
-       adpbuf[clen+24] = "1"; // assert reset to reboot
-       adpbuf[clen+25] = 8'h0a; // newline
+       if(FAST_LOAD==0) begin
+        adpbuf[12] = "U"; // set upload filesize (N bytes)
+        adpbuf[13] = " "; // only up to 1Mbyte for now!
+        adpbuf[14] = FNmap_hex_digit(codesize[19:16]); //
+        adpbuf[15] = FNmap_hex_digit(codesize[15:12]); //
+        adpbuf[16] = FNmap_hex_digit(codesize[11: 8]); //
+        adpbuf[17] = FNmap_hex_digit(codesize[ 7: 4]); //
+        adpbuf[18] = FNmap_hex_digit(codesize[ 3: 0]); //
+        adpbuf[19] = 8'h0a; // newline
+        $readmemh(CODEFILENAME, adpbuf, 20);
+        adpbuf[clen+20] = "C"; // control
+        adpbuf[clen+21] = " ";
+        adpbuf[clen+22] = "2"; // (gpio bit set)
+        adpbuf[clen+23] = "0";
+        adpbuf[clen+24] = "1"; // assert reset to reboot
+        adpbuf[clen+25] = 8'h0a; // newline
+       end else begin
+        clen = 0;
+        adpbuf[12] = "C"; // control
+        adpbuf[13] = " ";
+        adpbuf[14] = "2"; // (gpio bit set)
+        adpbuf[15] = "0";
+        adpbuf[16] = "1"; // assert reset to reboot
+        adpbuf[17] = 8'h0a; // newline
+       end
        // append any ADP command file to the code memory preload
        flen =0;
        fd= $fopen(TXDFILENAME,"r");